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Commit ad03d1f9 authored by Yaniv Gardi's avatar Yaniv Gardi Committed by David Keitel
Browse files

phy: relocate and rename phy ufs files 



This change contains:
1. Relocating the phy ufs files to reside under the phy driver since
this is the location of any file that implements the APIs presented in
the generic phy framework
2. Renaming ufs-msm-phy*.* files to be phy-qcom-ufs*.* files.
Since UFS is not used strictly in a specific set of targets but rather
its code is applicable to MSM, APQ, IPQ etc, any mentioning of "msm" in
the file name should be changed to "qcom".
Also, prefix of "phy-" is the naming convention of platform driver files
that reside in the phy driver.
3. As a result of the relocation of files into the phy driver,
a new path is created (include/linux/scsi/ufs) and there we expose ufs
header files that are being used also from the drivers/scsi/ufs
and from drivers/phy as well.

Change-Id: Ie5cb47718911ff711d9401a389f56fa508fcddf3
Signed-off-by: default avatarYaniv Gardi <ygardi@codeaurora.org>
[gbroner@codeaurora.org: fix merge conflicts]
Signed-off-by: default avatarGilad Broner <gbroner@codeaurora.org>
[venkatg@codeaurora.org: resolved merge conflicts by keeping
upstream version]
Signed-off-by: default avatarVenkat Gopalakrishnan <venkatg@codeaurora.org>
parent 948f549f

drivers/phy/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -36,6 +36,9 @@ obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o 
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o

obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o

obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o

obj-$(CONFIG_SCSI_UFS_QCOM) 	+= phy-qcom-ufs.o

obj-$(CONFIG_SCSI_UFS_QCOM) 	+= phy-qcom-ufs-qmp-28nm.o

obj-$(CONFIG_SCSI_UFS_QCOM) 	+= phy-qcom-ufs-qmp-20nm.o

obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o

obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o

obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o

drivers/phy/phy-qcom-ufs-qmp-20nm.c

+8 −22
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.

 * Copyright (c) 2013-2014, Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -17,40 +17,26 @@ 
#define UFS_PHY_NAME "ufs_phy_qmp_20nm"



static

int ufs_qcom_phy_qmp_20nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,

					bool is_rate_B)

int ufs_qcom_phy_qmp_20nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy)

{

	struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;

	int tbl_size_A, tbl_size_B;

	u8 major = ufs_qcom_phy->host_ctrl_rev_major;

	u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;

	u16 step = ufs_qcom_phy->host_ctrl_rev_step;

	int rate = UFS_QCOM_LIMIT_HS_RATE;

	int err;



	if ((major == 0x1) && (minor == 0x002) && (step == 0x0000)) {

		tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_2_0);

		tbl_A = phy_cal_table_rate_A_1_2_0;

	} else if ((major == 0x1) && (minor == 0x003) && (step == 0x0000)) {

		tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_3_0);

		tbl_A = phy_cal_table_rate_A_1_3_0;

	} else {

		dev_err(ufs_qcom_phy->dev, "%s: Unknown UFS-PHY version, no calibration values\n",

			__func__);

		err = -ENODEV;

		goto out;

	}

	tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);

	tbl_A = phy_cal_table_rate_A;



	tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);

	tbl_B = phy_cal_table_rate_B;



	err = ufs_qcom_phy_calibrate(ufs_qcom_phy, tbl_A, tbl_size_A,

						tbl_B, tbl_size_B, is_rate_B);

						tbl_B, tbl_size_B, rate);



	if (err)

		dev_err(ufs_qcom_phy->dev, "%s: ufs_qcom_phy_calibrate() failed %d\n",

			__func__, err);



out:

	return err;

}
@@ -171,7 +157,7 @@ static int ufs_qcom_phy_qmp_20nm_is_pcs_ready(struct ufs_qcom_phy *phy_common) 
	return err;

}



static const struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = {

struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = {

	.init		= ufs_qcom_phy_qmp_20nm_init,

	.exit		= ufs_qcom_phy_exit,

	.power_on	= ufs_qcom_phy_power_on,
@@ -179,7 +165,7 @@ static const struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = { 
	.owner		= THIS_MODULE,

};



static struct ufs_qcom_phy_specific_ops phy_20nm_ops = {

struct ufs_qcom_phy_specific_ops phy_20nm_ops = {

	.calibrate_phy		= ufs_qcom_phy_qmp_20nm_phy_calibrate,

	.start_serdes		= ufs_qcom_phy_qmp_20nm_start_serdes,

	.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_20nm_is_pcs_ready,

drivers/scsi/ufs/ufs-msm-phy-qmp-20nm.c→drivers/phy/phy-qcom-ufs-qmp-20nm.c~HEAD

+23 −21
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013-2014, Linux Foundation. All rights reserved.

 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -12,42 +12,45 @@ 
 *

 */



#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/time.h>

#include <linux/clk.h>

#include <linux/of.h>

#include <linux/iopoll.h>

#include <linux/platform_device.h>

#include <linux/msm-bus.h>



#include "ufs-msm-phy.h"

#include "ufs-msm-phy-qmp-20nm.h"

#include "phy-qcom-ufs-qmp-20nm.h"



#define UFS_PHY_NAME "ufs_phy_qmp_20nm"



static

int ufs_qcom_phy_qmp_20nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy)

int ufs_qcom_phy_qmp_20nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,

					bool is_rate_B)

{

	struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;

	int tbl_size_A, tbl_size_B;

	int rate = UFS_QCOM_LIMIT_HS_RATE;

	u8 major = ufs_qcom_phy->host_ctrl_rev_major;

	u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;

	u16 step = ufs_qcom_phy->host_ctrl_rev_step;

	int err;



	tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);

	tbl_A = phy_cal_table_rate_A;

	if ((major == 0x1) && (minor == 0x002) && (step == 0x0000)) {

		tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_2_0);

		tbl_A = phy_cal_table_rate_A_1_2_0;

	} else if ((major == 0x1) && (minor == 0x003) && (step == 0x0000)) {

		tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_3_0);

		tbl_A = phy_cal_table_rate_A_1_3_0;

	} else {

		dev_err(ufs_qcom_phy->dev, "%s: Unknown UFS-PHY version, no calibration values\n",

			__func__);

		err = -ENODEV;

		goto out;

	}



	tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);

	tbl_B = phy_cal_table_rate_B;



	err = ufs_qcom_phy_calibrate(ufs_qcom_phy, tbl_A, tbl_size_A,

						tbl_B, tbl_size_B, rate);

						tbl_B, tbl_size_B, is_rate_B);



	if (err)

		dev_err(ufs_qcom_phy->dev, "%s: ufs_qcom_phy_calibrate() failed %d\n",

			__func__, err);



out:

	return err;

}
@@ -168,7 +171,7 @@ static int ufs_qcom_phy_qmp_20nm_is_pcs_ready(struct ufs_qcom_phy *phy_common) 
	return err;

}



struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = {

static const struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = {

	.init		= ufs_qcom_phy_qmp_20nm_init,

	.exit		= ufs_qcom_phy_exit,

	.power_on	= ufs_qcom_phy_power_on,
@@ -176,7 +179,7 @@ struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = { 
	.owner		= THIS_MODULE,

};



struct ufs_qcom_phy_specific_ops phy_20nm_ops = {

static struct ufs_qcom_phy_specific_ops phy_20nm_ops = {

	.calibrate_phy		= ufs_qcom_phy_qmp_20nm_phy_calibrate,

	.start_serdes		= ufs_qcom_phy_qmp_20nm_start_serdes,

	.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_20nm_is_pcs_ready,
@@ -244,7 +247,6 @@ static struct platform_driver ufs_qcom_phy_qmp_20nm_driver = { 
	.driver = {

		.of_match_table = ufs_qcom_phy_qmp_20nm_of_match,

		.name = "ufs_qcom_phy_qmp_20nm",

		.owner = THIS_MODULE,

	},

};

drivers/phy/phy-qcom-ufs-qmp-20nm.h

+9 −28
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.

 * Copyright (c) 2013-2014, Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -30,7 +30,6 @@ 
#define QSERDES_COM_PLL_CNTRL			COM_OFF(0x14)

#define QSERDES_COM_PLL_IP_SETI			COM_OFF(0x24)

#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL	COM_OFF(0x28)

#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN		COM_OFF(0x30)

#define QSERDES_COM_PLL_CP_SETI			COM_OFF(0x34)

#define QSERDES_COM_PLL_IP_SETP			COM_OFF(0x38)

#define QSERDES_COM_PLL_CP_SETP			COM_OFF(0x3C)
@@ -44,8 +43,6 @@ 
#define QSERDES_COM_BGTC			COM_OFF(0xA0)

#define QSERDES_COM_DEC_START1			COM_OFF(0xAC)

#define QSERDES_COM_PLL_AMP_OS			COM_OFF(0xB0)

#define QSERDES_COM_RES_CODE_UP_OFFSET		COM_OFF(0xD8)

#define QSERDES_COM_RES_CODE_DN_OFFSET		COM_OFF(0xDC)

#define QSERDES_COM_DIV_FRAC_START1		COM_OFF(0x100)

#define QSERDES_COM_DIV_FRAC_START2		COM_OFF(0x104)

#define QSERDES_COM_DIV_FRAC_START3		COM_OFF(0x108)
@@ -101,7 +98,6 @@ 
#define UFS_PHY_RX_MIN_SAVE_CONFIG_TIME_CAPABILITY	PHY_OFF(0xE8)

#define UFS_PHY_RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY	PHY_OFF(0xFC)

#define UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY		PHY_OFF(0x100)

#define UFS_PHY_RX_SIGDET_CTRL3				PHY_OFF(0x14c)

#define UFS_PHY_RMMI_ATTR_CTRL			PHY_OFF(0x160)

#define UFS_PHY_RMMI_RX_CFGUPDT_L1	(1 << 7)

#define UFS_PHY_RMMI_TX_CFGUPDT_L1	(1 << 6)
@@ -131,9 +127,8 @@ struct ufs_qcom_phy_qmp_20nm { 
	struct ufs_qcom_phy common_cfg;

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_2_0[] = {

static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL3, 0x0D),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),
@@ -176,28 +171,24 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_2_0[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3),

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_3_0[] = {

static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL3, 0x0D),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1e),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL2, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
@@ -212,24 +203,14 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_3_0[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x2b),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x38),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x3c),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_UP_OFFSET, 0x02),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_DN_OFFSET, 0x02),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x1b),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x0f),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x40),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3),

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1e),

};



#endif

drivers/scsi/ufs/ufs-msm-phy-qmp-20nm.h→drivers/phy/phy-qcom-ufs-qmp-20nm.h~HEAD

+29 −10
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013-2014, Linux Foundation. All rights reserved.

 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -15,7 +15,7 @@ 
#ifndef UFS_QCOM_PHY_QMP_20NM_H_

#define UFS_QCOM_PHY_QMP_20NM_H_



#include "ufs-msm-phy.h"

#include "phy-qcom-ufs-i.h"



/* QCOM UFS PHY control registers */
@@ -30,6 +30,7 @@ 
#define QSERDES_COM_PLL_CNTRL			COM_OFF(0x14)

#define QSERDES_COM_PLL_IP_SETI			COM_OFF(0x24)

#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL	COM_OFF(0x28)

#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN		COM_OFF(0x30)

#define QSERDES_COM_PLL_CP_SETI			COM_OFF(0x34)

#define QSERDES_COM_PLL_IP_SETP			COM_OFF(0x38)

#define QSERDES_COM_PLL_CP_SETP			COM_OFF(0x3C)
@@ -43,6 +44,8 @@ 
#define QSERDES_COM_BGTC			COM_OFF(0xA0)

#define QSERDES_COM_DEC_START1			COM_OFF(0xAC)

#define QSERDES_COM_PLL_AMP_OS			COM_OFF(0xB0)

#define QSERDES_COM_RES_CODE_UP_OFFSET		COM_OFF(0xD8)

#define QSERDES_COM_RES_CODE_DN_OFFSET		COM_OFF(0xDC)

#define QSERDES_COM_DIV_FRAC_START1		COM_OFF(0x100)

#define QSERDES_COM_DIV_FRAC_START2		COM_OFF(0x104)

#define QSERDES_COM_DIV_FRAC_START3		COM_OFF(0x108)
@@ -98,6 +101,7 @@ 
#define UFS_PHY_RX_MIN_SAVE_CONFIG_TIME_CAPABILITY	PHY_OFF(0xE8)

#define UFS_PHY_RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY	PHY_OFF(0xFC)

#define UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY		PHY_OFF(0x100)

#define UFS_PHY_RX_SIGDET_CTRL3				PHY_OFF(0x14c)

#define UFS_PHY_RMMI_ATTR_CTRL			PHY_OFF(0x160)

#define UFS_PHY_RMMI_RX_CFGUPDT_L1	(1 << 7)

#define UFS_PHY_RMMI_TX_CFGUPDT_L1	(1 << 6)
@@ -127,8 +131,9 @@ struct ufs_qcom_phy_qmp_20nm { 
	struct ufs_qcom_phy common_cfg;

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {

static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_2_0[] = {

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL3, 0x0D),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),
@@ -171,24 +176,28 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3),

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {

static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_3_0[] = {

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL3, 0x0D),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1e),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL2, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
@@ -203,14 +212,24 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x1b),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x0f),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x2b),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x38),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x3c),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_UP_OFFSET, 0x02),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_DN_OFFSET, 0x02),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x40),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3),

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1e),

};



#endif