Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit acf13402 authored by raghavendra ambadas's avatar raghavendra ambadas Committed by Gerrit - the friendly Code Review server
Browse files

ARM: dts: msm8996: Add display nodes for 8996 target 



Add FB1, rotator, and WB node in msm8996 dtsi file

Change-Id: I26d471eb64b3a1ccaf2fb201c4d0baf6505cae17
Signed-off-by: default avatarRaghavendra Ambadas <rambad@codeaurora.org>
parent c2161416

arch/arm/boot/dts/qcom/msm8996-cv2x.dtsi

+2 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -148,6 +148,7 @@ 
/delete-node/ &mdss_mdp;

/delete-node/ &mdss_dsi;

/delete-node/ &msm_ext_disp;

/delete-node/ &msm_wb_disp;

/delete-node/ &mdss_hdmi_tx;

/delete-node/ &mdss_rotator;

/delete-node/ &routing;

arch/arm/boot/dts/qcom/msm8996-mdss.dtsi

+74 −62
Original line number Diff line number Diff line 
/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2017, 2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -14,8 +14,9 @@ 
	mdss_mdp: qcom,mdss_mdp@900000 {

		compatible = "qcom,mdss_mdp";

		reg = <0x00900000 0x90000>,

		      <0x009b0000 0x1040>;

		reg-names = "mdp_phys", "vbif_phys";

		      <0x009b0000 0x1040>,

		      <0x009b8000 0x1040>;

		reg-names = "mdp_phys", "vbif_phys", "vbif_nrt_phys";

		interrupts = <0 83 0>;

		interrupt-controller;

		#interrupt-cells = <1>;
@@ -66,10 +67,12 @@ 
					  0x00009000 0x0000B000>;

		qcom,mdss-pipe-rgb-off = <0x00015000 0x00017000

					  0x00019000 0x0001B000>;

		qcom,mdss-pipe-dma-off = <0x00025000 0x00027000>;

		qcom,mdss-pipe-cursor-off = <0x00035000 0x00037000>;



		qcom,mdss-pipe-vig-xin-id = <0 4 8 12>;

		qcom,mdss-pipe-rgb-xin-id = <1 5 9 13>;

		qcom,mdss-pipe-dma-xin-id = <2 10>;

		qcom,mdss-pipe-cursor-xin-id = <7 7>;



		/* These Offsets are relative to "mdp_phys + mdp-reg-offset" address */
@@ -81,16 +84,19 @@ 
						      <0x2B4 4 8>,

						      <0x2BC 4 8>,

						      <0x2C4 4 8>;

		qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2AC 8 12>,

						      <0x2B4 8 12>;

		qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3A8 16 15>,

							 <0x3B0 16 15>;





		qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400

				     0x00002600>;

				     0x00002600 0x00002800>;

		qcom,mdss-mixer-intf-off = <0x00045000 0x00046000

					0x00047000 0x0004A000>;

		qcom,mdss-mixer-wb-off = <0x00048000 0x00049000>;

		qcom,mdss-dspp-off = <0x00055000 0x00057000>;

		qcom,mdss-wb-off = <0x00066000>;

		qcom,mdss-wb-off = <0x00065000 0x00065800 0x00066000>;

		qcom,mdss-intf-off = <0x0006B000 0x0006B800

					0x0006C000 0x0006C800>;

		qcom,mdss-pingpong-off = <0x00071000 0x00071800
@@ -99,7 +105,6 @@ 
		qcom,mdss-ppb-ctl-off = <0x00000330 0x00000338>;

		qcom,mdss-ppb-cfg-off = <0x00000334 0x0000033C>;

		qcom,mdss-has-pingpong-split;

		qcom,mdss-has-separate-rotator;



		qcom,mdss-ad-off = <0x0079000 0x00079800 0x0007a000>;

		qcom,mdss-cdm-off = <0x0007a200>;
@@ -108,6 +113,9 @@ 
		qcom,mdss-has-source-split;

		qcom,mdss-highest-bank-bit = <0x2>;

		qcom,mdss-has-decimation;

		qcom,mdss-has-rotator-downscale;

		qcom,mdss-rot-downscale-min = <2>;

		qcom,mdss-rot-downscale-max = <16>;

		qcom,mdss-idle-power-collapse-enabled;

		clocks = <&clock_mmss clk_mdss_ahb_clk>,

			 <&clock_mmss clk_mdss_axi_clk>,
@@ -244,6 +252,19 @@ 
				"mdp_axi_clk";

		};



		smmu_rot_unsec: qcom,smmu_rot_unsec_cb {

			compatible = "qcom,smmu_rot_unsec";

			iommus = <&rot_smmu 0>;

			reg = <0x00d09000 0xd00>;

			reg-names = "mmu_cb";

			gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>;

			clocks = <&clock_mmss clk_smmu_rot_ahb_clk>,

				<&clock_mmss clk_mmagic_mdss_axi_clk>,

				<&clock_mmss clk_smmu_rot_axi_clk>;

			clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk",

				"rot_axi_clk";

		};



		smmu_mdp_sec: qcom,smmu_mdp_sec_cb {

			compatible = "qcom,smmu_mdp_sec";

			iommus = <&mdp_smmu 1>;
@@ -257,6 +278,19 @@ 
				"mdp_axi_clk";

		};



		smmu_rot_sec: qcom,smmu_rot_sec_cb {

			compatible = "qcom,smmu_rot_sec";

			iommus = <&rot_smmu 1>;

			reg = <0x00d0b000 0xd00>;

			reg-names = "mmu_cb";

			gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>;

			clocks = <&clock_mmss clk_smmu_rot_ahb_clk>,

				<&clock_mmss clk_mmagic_mdss_axi_clk>,

				<&clock_mmss clk_smmu_rot_axi_clk>;

			clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk",

				"rot_axi_clk";

		};



		mdss_fb0: qcom,mdss_fb_primary {

			cell-index = <0>;

			compatible = "qcom,mdss-fb";
@@ -265,6 +299,11 @@ 
			};

		};



		mdss_fb1: qcom,mdss_fb_wfd {

			cell-index = <1>;

			compatible = "qcom,mdss-fb";

		};



		mdss_fb2: qcom,mdss_fb_hdmi {

			cell-index = <2>;

			compatible = "qcom,mdss-fb";
@@ -386,11 +425,17 @@ 
				 <&mdss_dsi0_pll clk_dsi0pll_byte_clk_mux>,

				 <&mdss_dsi0_pll clk_dsi0pll_pixel_clk_mux>,

				 <&mdss_dsi0_pll clk_dsi0pll_byte_clk_src>,

				 <&mdss_dsi0_pll clk_dsi0pll_pixel_clk_src>;

				 <&mdss_dsi0_pll clk_dsi0pll_pixel_clk_src>,

				 <&mdss_dsi0_pll

					clk_dsi0pll_shadow_byte_clk_src>,

				 <&mdss_dsi0_pll

					clk_dsi0pll_shadow_pixel_clk_src>;

			clock-names = "byte_clk", "pixel_clk", "core_clk",

				"byte_clk_rcg", "pixel_clk_rcg",

				"pll_byte_clk_mux", "pll_pixel_clk_mux",

				"pll_byte_clk_src", "pll_pixel_clk_src";

				"pll_byte_clk_src", "pll_pixel_clk_src",

				"pll_shadow_byte_clk_src",

				"pll_shadow_pixel_clk_src";



			qcom,null-insertion-enabled;

			qcom,platform-strength-ctrl = [ff 06
@@ -430,12 +475,19 @@ 
				 <&clock_mmss clk_pclk1_clk_src>,

				 <&mdss_dsi0_pll clk_dsi0pll_byte_clk_mux>,

				 <&mdss_dsi0_pll clk_dsi0pll_pixel_clk_mux>,

				 <&mdss_dsi0_pll clk_dsi0pll_byte_clk_src>,

				 <&mdss_dsi0_pll clk_dsi0pll_pixel_clk_src>;

				 <&mdss_dsi1_pll clk_dsi1pll_byte_clk_src>,

				 <&mdss_dsi1_pll clk_dsi1pll_pixel_clk_src>,

				 <&mdss_dsi1_pll

					clk_dsi1pll_shadow_byte_clk_src>,

				 <&mdss_dsi1_pll

					clk_dsi1pll_shadow_pixel_clk_src>;

			clock-names = "byte_clk", "pixel_clk", "core_clk",

				"byte_clk_rcg", "pixel_clk_rcg",

				"pll_byte_clk_mux", "pll_pixel_clk_mux",

				"pll_byte_clk_src", "pll_pixel_clk_src";

				"pll_byte_clk_src", "pll_pixel_clk_src",

				"pll_byte_clk_src", "pll_pixel_clk_src",

				"pll_shadow_byte_clk_src",

				"pll_shadow_pixel_clk_src";



			qcom,null-insertion-enabled;

			qcom,platform-strength-ctrl = [ff 06
@@ -453,15 +505,15 @@ 
		};

	};



	qcom,mdss_wb_panel {

	msm_wb_disp: qcom,mdss_wb_panel {

		compatible = "qcom,mdss_wb";

		qcom,mdss_pan_res = <640 480>;

		qcom,mdss_pan_bpp = <24>;

		qcom,mdss-fb-map = <&mdss_fb1>;

	};



	msm_ext_disp: qcom,msm_ext_disp {

		compatible = "qcom,msm-ext-disp";



		ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {

			compatible = "qcom,msm-ext-disp-audio-codec-rx";

			qcom,msm_ext_disp = <&msm_ext_disp>;
@@ -485,14 +537,13 @@ 
		qcom,enable-load = <0>;

		qcom,disable-load = <0>;



		qcom,msm_ext_disp = <&msm_ext_disp>;

		clocks = <&clock_mmss clk_mdss_mdp_vote_clk>,

			 <&clock_mmss clk_mdss_ahb_clk>,

			 <&clock_mmss clk_mdss_hdmi_clk>,

			 <&clock_mmss clk_mdss_hdmi_ahb_clk>,

			 <&clock_mmss clk_mdss_extpclk_clk>;

		clock-names = "hpd_mdp_core_clk", "hpd_iface_clk",

			"hpd_core_clk", "hpd_alt_iface_clk", "core_extp_clk";

		clock-names = "mdp_core_clk", "iface_clk",

				"core_clk", "alt_iface_clk", "extp_clk";



		qcom,hdmi-tx-hpd = <&pm8994_mpps 4 0>;

		qcom,mdss-fb-map = <&mdss_fb2>;
@@ -504,15 +555,11 @@ 
	};



	mdss_rotator: qcom,mdss_rotator {

		compatible = "qcom,sde_rotator";

		reg = <0x00900000 0x90000>,

		      <0x009b8000 0x1040>;

		reg-names = "mdp_phys",

			"rot_vbif_phys";

		qcom,mdss-wb-count = <1>;

		qcom,mdss-wb-id = <0>;

		qcom,mdss-ctl-id = <4>;

		qcom,mdss-highest-bank-bit = <0x2>;

		compatible = "qcom,mdss_rotator";

		qcom,mdss-wb-count = <2>;

		qcom,mdss-has-downscale;

		qcom,mdss-has-ubwc;

		qcom,mdss-has-reg-bus;

		/* Bus Scale Settings */

		qcom,msm-bus,name = "mdss_rotator";

		qcom,msm-bus,num-cases = <3>;
@@ -528,42 +575,7 @@ 
		qcom,supply-names = "rot-mmagic-mdss-gdsc", "rot-vdd";



		clocks = <&clock_mmss clk_mmss_misc_ahb_clk>,

			<&clock_mmss clk_mdss_rotator_vote_clk>,

			<&clock_mmss clk_mdss_ahb_clk>,

			<&clock_mmss clk_mdss_axi_clk>,

			<&clock_mmss clk_mdp_clk_src>;

		clock-names = "iface_clk", "rot_core_clk",

			"mdss_ahb_clk", "mdss_axi_clk", "mdp_clk_src";



		interrupt-parent = <&mdss_mdp>;

		interrupts = <32 0>;



		/* VBIF QoS remapper settings*/

		qcom,mdss-rot-vbif-qos-setting = <1 1 1 1>;



		qcom,mdss-default-ot-rd-limit = <32>;

		qcom,mdss-default-ot-wr-limit = <16>;



		smmu_rot_unsecure: qcom,smmu_rot_unsec_cb {

			compatible = "qcom,smmu_sde_rot_unsec";

			iommus = <&rot_smmu 0>;

			gdsc-mdss-supply = <&gdsc_mmagic_mdss>;

			clocks = <&clock_mmss clk_smmu_rot_ahb_clk>,

				<&clock_mmss clk_mmagic_mdss_axi_clk>,

				<&clock_mmss clk_smmu_rot_axi_clk>;

			clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk",

				"rot_axi_clk";

		};



		smmu_rot_secure: qcom,smmu_rot_sec_cb {

			compatible = "qcom,smmu_sde_rot_sec";

			iommus = <&rot_smmu 1>;

			gdsc-mdss-supply = <&gdsc_mmagic_mdss>;

			clocks = <&clock_mmss clk_smmu_rot_ahb_clk>,

				<&clock_mmss clk_mmagic_mdss_axi_clk>,

				<&clock_mmss clk_smmu_rot_axi_clk>;

			clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk",

				"rot_axi_clk";

		};

			<&clock_mmss clk_mdss_rotator_vote_clk>;

		clock-names = "iface_clk", "rot_core_clk";

	};

};