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Commit abcf426a authored by Mukesh Kumar Savaliya's avatar Mukesh Kumar Savaliya
Browse files

ARM: dts: msm: specify UART configuration on msmfalcon. 



Initial support for all BLSP UARTs with default configuration
and disabled state such that clients can overwrite and enable
respective UART instance as per need.

Change-Id: I15ef73049cee76c6ea5b3916d9281bbd9fdfc563
Signed-off-by: default avatarMukesh Kumar Savaliya <msavaliy@codeaurora.org>
parent 1e170076

arch/arm/boot/dts/qcom/msmfalcon-blsp.dtsi

+148 −0
Original line number Diff line number Diff line
@@ -226,4 +226,152 @@ 
			 <&clock_gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>;

		status = "disabled";

	};



	blsp1_uart1_hs: uart@c16f000 { /* BLSP1 UART1 */

		compatible = "qcom,msm-hsuart-v14";

		reg = <0xc16f000 0x200>,

		    <0xc144000 0x1f000>;

		reg-names = "core_mem", "bam_mem";

		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";

		#address-cells = <0>;

		interrupt-parent = <&blsp1_uart1_hs>;

		interrupts = <0 1 2>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 0 107 0

			    1 &intc 0 0 238 0

			    2 &tlmm 1 0>;



		qcom,inject-rx-on-wakeup;

		qcom,rx-char-to-inject = <0xfd>;



		qcom,bam-tx-ep-pipe-index = <0>;

		qcom,bam-rx-ep-pipe-index = <1>;

		qcom,master-id = <86>;

		clock-names = "core_clk", "iface_clk";

		clocks = <&clock_gcc GCC_BLSP1_UART1_APPS_CLK>,

		    <&clock_gcc GCC_BLSP1_AHB_CLK>;

		pinctrl-names = "sleep", "default";

		pinctrl-0 = <&blsp1_uart1_sleep>;

		pinctrl-1 = <&blsp1_uart1_active>;



		qcom,msm-bus,name = "buart1";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			    <86 512 0 0>,

			    <86 512 500 800>;

		status = "disabled";

	};



	blsp1_uart2_hs: uart@c170000 { /* BLSP1 UART2 */

		compatible = "qcom,msm-hsuart-v14";

		reg = <0xc170000 0x200>,

		    <0xc144000 0x1f000>;

		reg-names = "core_mem", "bam_mem";

		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";

		#address-cells = <0>;

		interrupt-parent = <&blsp1_uart2_hs>;

		interrupts = <0 1 2>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 0 108 0

			    1 &intc 0 0 238 0

			    2 &tlmm 5 0>;



		qcom,inject-rx-on-wakeup;

		qcom,rx-char-to-inject = <0xfd>;



		qcom,bam-tx-ep-pipe-index = <2>;

		qcom,bam-rx-ep-pipe-index = <3>;

		qcom,master-id = <86>;

		clock-names = "core_clk", "iface_clk";

		clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,

		    <&clock_gcc GCC_BLSP1_AHB_CLK>;

		pinctrl-names = "sleep", "default";

		pinctrl-0 = <&blsp1_uart2_sleep>;

		pinctrl-1 = <&blsp1_uart2_active>;



		qcom,msm-bus,name = "buart2";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			    <86 512 0 0>,

			    <86 512 500 800>;

		status = "disabled";

	};



	blsp2_uart1_hs: uart@c1af000 { /* BLSP2 UART1 */

		compatible = "qcom,msm-hsuart-v14";

		reg = <0xc1af000 0x200>,

		    <0xc184000 0x1f000>;

		reg-names = "core_mem", "bam_mem";

		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";

		#address-cells = <0>;

		interrupt-parent = <&blsp2_uart1_hs>;

		interrupts = <0 1 2>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 0 113 0

			    1 &intc 0 0 239 0

			    2 &tlmm 17 0>;



		qcom,inject-rx-on-wakeup;

		qcom,rx-char-to-inject = <0xfd>;



		qcom,bam-tx-ep-pipe-index = <0>;

		qcom,bam-rx-ep-pipe-index = <1>;

		qcom,master-id = <84>;

		clock-names = "core_clk", "iface_clk";

		clocks = <&clock_gcc GCC_BLSP2_UART1_APPS_CLK>,

		    <&clock_gcc GCC_BLSP2_AHB_CLK>;

		pinctrl-names = "sleep", "default";

		pinctrl-0 = <&blsp2_uart1_sleep>;

		pinctrl-1 = <&blsp2_uart1_active>;



		qcom,msm-bus,name = "buart3";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			    <84 512 0 0>,

			    <84 512 500 800>;

		status = "disabled";

	};



	blsp2_uart2_hs: uart@c1b0000 { /* BLSP2 UART2 */

		compatible = "qcom,msm-hsuart-v14";

		reg = <0xc1b0000 0x200>,

		    <0xc184000 0x1f000>;

		reg-names = "core_mem", "bam_mem";

		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";

		#address-cells = <0>;

		interrupt-parent = <&blsp2_uart2_hs>;

		interrupts = <0 1 2>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 0 114 0

			    1 &intc 0 0 239 0

			    2 &tlmm 25 0>;



		qcom,inject-rx-on-wakeup;

		qcom,rx-char-to-inject = <0xfd>;



		qcom,bam-tx-ep-pipe-index = <2>;

		qcom,bam-rx-ep-pipe-index = <3>;

		qcom,master-id = <84>;

		clock-names = "core_clk", "iface_clk";

		clocks = <&clock_gcc GCC_BLSP2_UART2_APPS_CLK>,

		    <&clock_gcc GCC_BLSP2_AHB_CLK>;

		pinctrl-names = "sleep", "default";

		pinctrl-0 = <&blsp2_uart2_sleep>;

		pinctrl-1 = <&blsp2_uart2_active>;



		qcom,msm-bus,name = "buart4";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			    <84 512 0 0>,

			    <84 512 500 800>;

		status = "disabled";

	};

};

arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi

+105 −0
Original line number Diff line number Diff line
@@ -369,5 +369,110 @@ 
				};

			};

		};



		/* HS UART CONFIGURATION */

		blsp1_uart1_active: blsp1_uart1_active {

			mux {

				pins = "gpio0", "gpio1", "gpio2", "gpio3";

				function = "blsp_uart1";

			};



			config {

				pins = "gpio0", "gpio1", "gpio2", "gpio3";

				drive-strength = <2>;

				bias-disable;

			};

		};



		blsp1_uart1_sleep: blsp1_uart1_sleep {

			mux {

				pins = "gpio0", "gpio1", "gpio2", "gpio3";

				function = "gpio";

			};



			config {

				pins = "gpio0", "gpio1", "gpio2", "gpio3";

				drive-strength = <2>;

				bias-disable;

			};

		};



		blsp1_uart2_active: blsp1_uart2_active {

			mux {

				pins = "gpio4", "gpio5", "gpio6", "gpio7";

				function = "blsp_uart2 ";

			};



			config {

				pins = "gpio4", "gpio5", "gpio6", "gpio7";

				drive-strength = <2>;

				bias-disable;

			};

		};



		blsp1_uart2_sleep: blsp1_uart2_sleep {

			mux {

				pins = "gpio4", "gpio5", "gpio6", "gpio7";

				function = "gpio";

			};



			config {

				pins = "gpio4", "gpio5", "gpio6", "gpio7";

				drive-strength = <2>;

				bias-disable;

			};

		};



		blsp2_uart1_active: blsp2_uart1_active {

			mux {

				pins = "gpio16", "gpio17", "gpio18", "gpio19";

				function = "blsp_uart5";

			};



			config {

				pins = "gpio16", "gpio17", "gpio18", "gpio19";

				drive-strength = <2>;

				bias-disable;

			};

		};



		blsp2_uart1_sleep: blsp2_uart1_sleep {

			mux {

				pins = "gpio16", "gpio17", "gpio18", "gpio19";

				function = "gpio";

			};



			config {

				pins = "gpio16", "gpio17", "gpio18", "gpio19";

				drive-strength = <2>;

				bias-disable;

			};

		};



		blsp2_uart2_active: blsp2_uart2_active {

			mux {

				pins = "gpio24", "gpio25", "gpio26", "gpio27";

				function = "blsp_uart6_a";

			};



			config {

				pins = "gpio24", "gpio25", "gpio26", "gpio27";

				drive-strength = <2>;

				bias-disable;

			};

		};



		blsp2_uart2_sleep: blsp2_uart2_sleep {

			mux {

				pins = "gpio24", "gpio25", "gpio26", "gpio27";

				function = "gpio";

			};



			config {

				pins = "gpio24", "gpio25", "gpio26", "gpio27";

				drive-strength = <2>;

				bias-disable;

			};

		};

	};

};