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Commit aa66bb7c authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: Update the GPU PLL configuration to 800MHz 



The GPU PLL initial configuration is modified to 800MHz and also update the
RCG to be able to support force enable/disable for gfx3d_clk_src.

Change-Id: I8e6d7dba762b678070d66e291347af2cdf804ae5
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent fb1e5793

drivers/clk/qcom/clk-rcg2.c

+2 −0
Original line number Diff line number Diff line
@@ -935,6 +935,8 @@ static int clk_gfx3d_src_set_rate_and_parent(struct clk_hw *hw, 
}



const struct clk_ops clk_gfx3d_src_ops = {

	.enable = clk_rcg2_enable,

	.disable = clk_rcg2_disable,

	.is_enabled = clk_rcg2_is_enabled,

	.get_parent = clk_rcg2_get_parent,

	.set_parent = clk_rcg2_set_parent,

drivers/clk/qcom/gpucc-msmfalcon.c

+4 −4
Original line number Diff line number Diff line
@@ -84,12 +84,12 @@ static struct pll_vco gpu_vco[] = { 
	{ 250000000,   500000000, 3 },

};



/* 640MHz configuration */

/* 800MHz configuration */

static const struct pll_config gpu_pll0_config = {

	.l = 0x21,

	.l = 0x29,

	.config_ctl_val = 0x4001055b,

	.alpha = 0x55555600,

	.alpha_u = 0x55,

	.alpha = 0xaaaaab00,

	.alpha_u = 0xaa,

	.alpha_en_mask = BIT(24),

	.vco_val = 0x2 << 20,

	.vco_mask = 0x3 << 20,