Merge "ARM: dts: msm: add mdss node for sdm630" (a9868ae5) · Commits · e / devices / android_kernel_sony_msm8998

Documentation/devicetree/bindings/fb/mdss-pll.txt

+1 −1

Original line number	Diff line number	Diff line
		@@ -16,7 +16,7 @@ Required properties:
		"qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8",
		"qcom,mdss_dsi_pll_8998", "qcom,mdss_dp_pll_8998",
		"qcom,mdss_hdmi_pll_8998", "qcom,mdss_dsi_pll_sdm660",
		"qcom,mdss_dp_pll_sdm660"
		"qcom,mdss_dp_pll_sdm660", "qcom,mdss_dsi_pll_sdm630"
		- cell-index: Specifies the controller used
		- reg: offset and length of the register set for the device.
		- reg-names : names to refer to register sets related to this device

arch/arm/boot/dts/qcom/sdm630-cdp.dtsi

+35 −0

Original line number	Diff line number	Diff line
		@@ -101,3 +101,38 @@

		status = "ok";
		};

		&mdss_mdp {
		qcom,mdss-pref-prim-intf = "dsi";
		};

		&mdss_dsi {
		hw-config = "single_dsi";
		};

		&mdss_dsi0 {
		qcom,dsi-pref-prim-pan = <&dsi_nt35695b_truly_fhd_video>;
		pinctrl-names = "mdss_default", "mdss_sleep";
		pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
		pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
		qcom,platform-reset-gpio = <&tlmm 53 0>;
		qcom,platform-te-gpio = <&tlmm 59 0>;
		};

		&pm660l_wled {
		qcom,led-strings-list = [01 02];
		};

		&dsi_nt35695b_truly_fhd_video {
		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
		qcom,mdss-dsi-bl-min-level = <1>;
		qcom,mdss-dsi-bl-max-level = <4095>;
		qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
		};

		&dsi_nt35695b_truly_fhd_cmd {
		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
		qcom,mdss-dsi-bl-min-level = <1>;
		qcom,mdss-dsi-bl-max-level = <4095>;
		qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
		};

arch/arm/boot/dts/qcom/sdm630-mdss-panels.dtsi

0 → 100644

+66 −0

Original line number	Diff line number	Diff line
		/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include "dsi-panel-sim-video.dtsi"
		#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
		#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"

		&soc {
		dsi_panel_pwr_supply: dsi_panel_pwr_supply {
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,panel-supply-entry@0 {
		reg = <0>;
		qcom,supply-name = "wqhd-vddio";
		qcom,supply-min-voltage = <1880000>;
		qcom,supply-max-voltage = <1950000>;
		qcom,supply-enable-load = <32000>;
		qcom,supply-disable-load = <80>;
		};

		qcom,panel-supply-entry@1 {
		reg = <1>;
		qcom,supply-name = "lab";
		qcom,supply-min-voltage = <4600000>;
		qcom,supply-max-voltage = <6000000>;
		qcom,supply-enable-load = <100000>;
		qcom,supply-disable-load = <100>;
		};

		qcom,panel-supply-entry@2 {
		reg = <2>;
		qcom,supply-name = "ibb";
		qcom,supply-min-voltage = <4600000>;
		qcom,supply-max-voltage = <6000000>;
		qcom,supply-enable-load = <100000>;
		qcom,supply-disable-load = <100>;
		qcom,supply-post-on-sleep = <10>;
		};
		};
		};

		&dsi_nt35695b_truly_fhd_video {
		qcom,mdss-dsi-panel-timings-phy-v2 = [24 1e 08 09 05 03 04 a0
		24 1e 08 09 05 03 04 a0
		24 1e 08 09 05 03 04 a0
		24 1e 08 09 05 03 04 a0
		24 1a 08 09 05 03 04 a0];
		};

		&dsi_nt35695b_truly_fhd_cmd {
		qcom,mdss-dsi-panel-timings-phy-v2 = [24 1e 08 09 05 03 04 a0
		24 1e 08 09 05 03 04 a0
		24 1e 08 09 05 03 04 a0
		24 1e 08 09 05 03 04 a0
		24 1a 08 09 05 03 04 a0];
		};

arch/arm/boot/dts/qcom/sdm630-mdss-pll.dtsi

0 → 100644

+47 −0

Original line number	Diff line number	Diff line
		/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		&soc {
		mdss_dsi0_pll: qcom,mdss_dsi_pll@c994400 {
		compatible = "qcom,mdss_dsi_pll_sdm630";
		status = "ok";
		label = "MDSS DSI 0 PLL";
		cell-index = <0>;
		#clock-cells = <1>;

		reg = <0xc994400 0x588>,
		<0xc8c2300 0x8>;
		reg-names = "pll_base", "gdsc_base";

		gdsc-supply = <&gdsc_mdss>;

		clocks = <&clock_mmss MMSS_MDSS_AHB_CLK>;
		clock-names = "iface_clk";
		clock-rate = <0>;
		qcom,dsi-pll-ssc-en;
		qcom,dsi-pll-ssc-mode = "down-spread";

		qcom,platform-supply-entries {
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,platform-supply-entry@0 {
		reg = <0>;
		qcom,supply-name = "gdsc";
		qcom,supply-min-voltage = <0>;
		qcom,supply-max-voltage = <0>;
		qcom,supply-enable-load = <0>;
		qcom,supply-disable-load = <0>;
		};
		};
		};
		};

arch/arm/boot/dts/qcom/sdm630-mdss.dtsi

0 → 100644

+488 −0

Original line number	Diff line number	Diff line
		/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <dt-bindings/clock/mdss-pll-clk.h>

		&soc {
		mdss_mdp: qcom,mdss_mdp@c900000 {
		compatible = "qcom,mdss_mdp";
		status = "ok";
		reg = <0x0c900000 0x90000>,
		<0x0c9b0000 0x1040>;
		reg-names = "mdp_phys", "vbif_phys";
		interrupts = <0 83 0>;
		interrupt-controller;
		#interrupt-cells = <1>;
		vdd-supply = <&gdsc_mdss>;

		/* Bus Scale Settings */
		qcom,msm-bus,name = "mdss_mdp";
		qcom,msm-bus,num-cases = <3>;
		qcom,msm-bus,num-paths = <2>;
		qcom,msm-bus,vectors-KBps =
		<22 512 0 0>, <23 512 0 0>,
		<22 512 0 6400000>, <23 512 0 6400000>,
		<22 512 0 6400000>, <23 512 0 6400000>;

		/* Fudge factors */
		qcom,mdss-ab-factor = <1 1>; /* 1 time */
		qcom,mdss-ib-factor = <1 1>; /* 1 time */
		qcom,mdss-clk-factor = <105 100>; /* 1.05 times */

		qcom,max-mixer-width = <2560>;
		qcom,max-pipe-width = <2560>;

		qcom,max-dest-scaler-input-width = <2048>;
		qcom,max-dest-scaler-output-width = <2560>;

		/* VBIF QoS remapper settings*/
		qcom,mdss-vbif-qos-rt-setting = <1 2 2 2>;
		qcom,mdss-vbif-qos-nrt-setting = <1 1 1 1>;
		qcom,vbif-settings = <0x00ac 0x00008040>,
		<0x00d0 0x00002828>;

		qcom,mdss-has-panic-ctrl;
		qcom,mdss-per-pipe-panic-luts = <0x000f>,
		<0xffff>,
		<0xfffc>,
		<0xff00>;

		qcom,mdss-mdp-reg-offset = <0x00001000>;
		qcom,max-bandwidth-low-kbps = <4100000>;
		qcom,max-bandwidth-high-kbps = <4100000>;
		qcom,max-bandwidth-per-pipe-kbps = <1 3200000>, /* Default */
		<2 2400000>; /* Camera */
		qcom,max-clk-rate = <412500000>;
		qcom,mdss-default-ot-rd-limit = <32>;
		qcom,mdss-default-ot-wr-limit = <40>;
		qcom,mdss-dram-channels = <2>;

		/* Bandwidth limit settings */
		qcom,max-bw-settings = <1 4100000>, /* Default */
		<2 3000000>; /* Camera */

		qcom,mdss-pipe-vig-off = <0x00005000>;
		qcom,mdss-pipe-dma-off = <0x00025000 0x00027000 0x00029000>;
		qcom,mdss-pipe-cursor-off = <0x00035000>;

		qcom,mdss-pipe-vig-xin-id = <0>;
		qcom,mdss-pipe-dma-xin-id = <1 5 9>;
		qcom,mdss-pipe-cursor-xin-id = <2>;

		/*
		* These Offsets are relative to
		* "mdp_phys + mdp-reg-offset" address
		*/
		qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2ac 0 0>;
		qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2ac 8 12>,
		<0x2b4 8 12>,
		<0x2c4 8 12>;
		qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3a8 16 15>;

		qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400
		0x00002600 0x00002800>;
		qcom,mdss-mixer-intf-off = <0x00045000 0x00047000>;
		qcom,mdss-dspp-off = <0x00055000>;
		qcom,mdss-wb-off = <0x00066000>;
		qcom,mdss-intf-off = <0x0006b000 0x0006b800>;
		qcom,mdss-pingpong-off = <0x00071000 0x00072000>;
		qcom,mdss-slave-pingpong-off = <0x00073000>;
		qcom,mdss-ppb-ctl-off = <0x00000330 0x00000338 0x00000370
		0x00000374> ;
		qcom,mdss-ppb-cfg-off = <0x00000334 0x0000033C>;
		qcom,mdss-has-pingpong-split;
		qcom,mdss-has-separate-rotator;

		qcom,mdss-ad-off = <0x0079000 0x00079800>;
		qcom,mdss-cdm-off = <0x0007a200>;
		qcom,mdss-wfd-mode = "intf";
		qcom,mdss-has-source-split;
		qcom,mdss-highest-bank-bit = <0x1>;
		qcom,mdss-has-decimation;
		qcom,mdss-idle-power-collapse-enabled;
		clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>,
		<&clock_mmss MMSS_MDSS_AHB_CLK>,
		<&clock_mmss MMSS_MDSS_AXI_CLK>,
		<&clock_mmss MDP_CLK_SRC>,
		<&clock_mmss MMSS_MDSS_MDP_CLK>,
		<&clock_mmss MMSS_MDSS_VSYNC_CLK>,
		<&clock_mmss MDP_CLK_SRC>;
		clock-names = "mnoc_clk", "iface_clk", "bus_clk",
		"core_clk_src", "core_clk", "vsync_clk",
		"lut_clk";

		qcom,mdp-settings = <0x01190 0x00000000>,
		<0x012ac 0xc0000ccc>,
		<0x012b4 0xc0000ccc>,
		<0x012bc 0x00cccccc>,
		<0x012c4 0x0000cccc>,
		<0x013a8 0x0cccc0c0>,
		<0x013b0 0xccccc0c0>,
		<0x013b8 0xcccc0000>,
		<0x013d0 0x00cc0000>,
		<0x0506c 0x00000000>,
		<0x0706c 0x00000000>,
		<0x0906c 0x00000000>,
		<0x0b06c 0x00000000>,
		<0x1506c 0x00000000>,
		<0x1706c 0x00000000>,
		<0x1906c 0x00000000>,
		<0x1b06c 0x00000000>,
		<0x2506c 0x00000000>,
		<0x2706c 0x00000000>;

		qcom,regs-dump-mdp = <0x01000 0x01458>,
		<0x02000 0x02094>,
		<0x02200 0x02294>,
		<0x02400 0x02494>,
		<0x02600 0x02694>,
		<0x02800 0x02894>,
		<0x05000 0x05154>,
		<0x05a00 0x05b00>,
		<0x25000 0x25184>,
		<0x27000 0x27184>,
		<0x29000 0x29184>,
		<0x35000 0x35150>,
		<0x45000 0x452bc>,
		<0x47000 0x472bc>,
		<0x55000 0x5522c>,
		<0x66000 0x662c0>,
		<0x6b000 0x6b268>,
		<0x6b800 0x6ba68>,
		<0x71000 0x710d4>,
		<0x72000 0x720d4>;

		qcom,regs-dump-names-mdp = "MDP",
		"CTL_0", "CTL_1", "CTL_2", "CTL_3", "CTL_4",
		"VIG0_SSPP", "VIG0",
		"DMA0_SSPP", "DMA1_SSPP","DMA2_SSPP",
		"CURSOR0_SSPP",
		"LAYER_0", "LAYER_2",
		"DSPP_0",
		"WB_2",
		"INTF_0", "INTF_1",
		"PP_0", "PP_2";

		/* buffer parameters to calculate prefill bandwidth */
		qcom,mdss-prefill-outstanding-buffer-bytes = <0>;
		qcom,mdss-prefill-y-buffer-bytes = <0>;
		qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>;
		qcom,mdss-prefill-scaler-buffer-lines-caf = <4>;
		qcom,mdss-prefill-post-scaler-buffer-pixels = <2560>;
		qcom,mdss-prefill-pingpong-buffer-pixels = <5120>;

		qcom,mdss-pp-offsets {
		qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>;
		qcom,mdss-sspp-vig-pcc-off = <0x1b00>;
		qcom,mdss-sspp-rgb-pcc-off = <0x380>;
		qcom,mdss-sspp-dma-pcc-off = <0x380>;
		qcom,mdss-lm-pgc-off = <0x3c0>;
		qcom,mdss-dspp-gamut-off = <0x1600>;
		qcom,mdss-dspp-pcc-off = <0x1700>;
		qcom,mdss-dspp-pgc-off = <0x17c0>;
		};

		qcom,mdss-scaler-offsets {
		qcom,mdss-vig-scaler-off = <0xa00>;
		qcom,mdss-vig-scaler-lut-off = <0xb00>;
		qcom,mdss-has-dest-scaler;
		qcom,mdss-dest-block-off = <0x00061000>;
		qcom,mdss-dest-scaler-off = <0x800 0x1000>;
		qcom,mdss-dest-scaler-lut-off = <0x900 0x1100>;
		};

		smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb {
		compatible = "qcom,smmu_mdp_unsec";
		iommus = <&mmss_bimc_smmu 0>;
		gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>;
		clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>,
		<&clock_mmss MMSS_MNOC_AHB_CLK>,
		<&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
		<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
		clock-names = "mmss_noc_axi_clk",
		"mmss_noc_ahb_clk",
		"mmss_smmu_ahb_clk",
		"mmss_smmu_axi_clk";
		};

		smmu_mdp_sec: qcom,smmu_mdp_sec_cb {
		compatible = "qcom,smmu_mdp_sec";
		iommus = <&mmss_bimc_smmu 1>;
		gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>;
		clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>,
		<&clock_mmss MMSS_MNOC_AHB_CLK>,
		<&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
		<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
		clock-names = "mmss_noc_axi_clk",
		"mmss_noc_ahb_clk",
		"mmss_smmu_ahb_clk",
		"mmss_smmu_axi_clk";
		};

		mdss_fb0: qcom,mdss_fb_primary {
		cell-index = <0>;
		compatible = "qcom,mdss-fb";
		};

		mdss_fb1: qcom,mdss_fb_wfd {
		cell-index = <1>;
		compatible = "qcom,mdss-fb";
		};

		mdss_fb2: qcom,mdss_fb_dp {
		cell-index = <2>;
		compatible = "qcom,mdss-fb";
		qcom,mdss-intf = <&mdss_dp_ctrl>;
		};
		};

		mdss_dsi: qcom,mdss_dsi@0 {
		compatible = "qcom,mdss-dsi";
		#address-cells = <1>;
		#size-cells = <1>;
		gdsc-supply = <&gdsc_mdss>;
		vdda-1p2-supply = <&pm660_l1>;
		vdda-0p9-supply = <&pm660l_l1>;
		ranges = <0xc994000 0xc994000 0x400
		0xc994400 0xc994400 0x588
		0xc828000 0xc828000 0xac>;

		/* Bus Scale Settings */
		qcom,msm-bus,name = "mdss_dsi";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<22 512 0 0>,
		<22 512 0 1000>;

		qcom,mmss-ulp-clamp-ctrl-offset = <0x14>;

		clocks = <&clock_mmss MMSS_MDSS_MDP_CLK>,
		<&clock_mmss MMSS_MNOC_AHB_CLK>,
		<&clock_mmss MMSS_MDSS_AHB_CLK>,
		<&clock_mmss MMSS_MDSS_AXI_CLK>,
		<&clock_mmss MMSS_MISC_AHB_CLK>,
		<&mdss_dsi0_pll BYTE0_MUX_CLK>,
		<&mdss_dsi0_pll PIX0_MUX_CLK>;
		clock-names = "mdp_core_clk",
		"mnoc_clk", "iface_clk",
		"bus_clk", "core_mmss_clk",
		"ext_byte0_clk","ext_pixel0_clk";

		qcom,core-supply-entries {
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,core-supply-entry@0 {
		reg = <0>;
		qcom,supply-name = "gdsc";
		qcom,supply-min-voltage = <0>;
		qcom,supply-max-voltage = <0>;
		qcom,supply-enable-load = <0>;
		qcom,supply-disable-load = <0>;
		};
		};

		qcom,ctrl-supply-entries {
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,ctrl-supply-entry@0 {
		reg = <0>;
		qcom,supply-name = "vdda-1p2";
		qcom,supply-min-voltage = <1200000>;
		qcom,supply-max-voltage = <1250000>;
		qcom,supply-enable-load = <12560>;
		qcom,supply-disable-load = <4>;
		};
		};

		qcom,phy-supply-entries {
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,phy-supply-entry@0 {
		reg = <0>;
		qcom,supply-name = "vdda-0p9";
		qcom,supply-min-voltage = <880000>;
		qcom,supply-max-voltage = <925000>;
		qcom,supply-enable-load = <73400>;
		qcom,supply-disable-load = <32>;
		};
		};

		mdss_dsi0: qcom,mdss_dsi_ctrl0@c994000 {
		compatible = "qcom,mdss-dsi-ctrl";
		label = "MDSS DSI CTRL->0";
		cell-index = <0>;
		reg = <0xc994000 0x400>,
		<0xc994400 0x588>,
		<0xc828000 0xac>;
		reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";

		qcom,timing-db-mode;
		wqhd-vddio-supply = <&pm660_l11>;
		lab-supply = <&lcdb_ldo_vreg>;
		ibb-supply = <&lcdb_ncp_vreg>;
		qcom,mdss-mdp = <&mdss_mdp>;
		qcom,mdss-fb-map = <&mdss_fb0>;

		clocks = <&clock_mmss MMSS_MDSS_BYTE0_CLK>,
		<&clock_mmss MMSS_MDSS_PCLK0_CLK>,
		<&clock_mmss MMSS_MDSS_ESC0_CLK>,
		<&clock_mmss BYTE0_CLK_SRC>,
		<&clock_mmss PCLK0_CLK_SRC>,
		<&clock_mmss MMSS_MDSS_BYTE0_INTF_CLK>;
		clock-names = "byte_clk", "pixel_clk", "core_clk",
		"byte_clk_rcg", "pixel_clk_rcg",
		"byte_intf_clk";

		qcom,platform-strength-ctrl = [ff 06
		ff 06
		ff 06
		ff 06
		ff 00];
		qcom,platform-regulator-settings = [1d
		1d 1d 1d 1d];
		qcom,platform-lane-config = [00 00 10 0f
		00 00 10 0f
		00 00 10 0f
		00 00 10 0f
		00 00 10 8f];
		};
		};

		qcom,mdss_wb_panel {
		compatible = "qcom,mdss_wb";
		qcom,mdss_pan_res = <640 480>;
		qcom,mdss_pan_bpp = <24>;
		qcom,mdss-fb-map = <&mdss_fb1>;
		};

		msm_ext_disp: qcom,msm_ext_disp {
		status = "disabled";
		compatible = "qcom,msm-ext-disp";

		ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
		compatible = "qcom,msm-ext-disp-audio-codec-rx";
		qcom,msm_ext_disp = <&msm_ext_disp>;
		};
		};

		mdss_dp_ctrl: qcom,dp_ctrl@c990000 {
		status = "disabled";
		cell-index = <0>;
		compatible = "qcom,mdss-dp";
		qcom,mdss-fb-map = <&mdss_fb2>;

		gdsc-supply = <&gdsc_mdss>;
		vdda-1p2-supply = <&pm660_l1>;
		vdda-0p9-supply = <&pm660l_l1>;

		reg = <0xc990000 0xa84>,
		<0xc011000 0x910>,
		<0x1fcb200 0x050>,
		<0xc8c2200 0x1a0>,
		<0x780000 0x621c>,
		<0xc9e1000 0x02c>;
		reg-names = "dp_ctrl", "dp_phy", "tcsr_regs", "dp_mmss_cc",
		"qfprom_physical","hdcp_physical";

		qcom,msm_ext_disp = <&msm_ext_disp>;

		qcom,core-supply-entries {
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,core-supply-entry@0 {
		reg = <0>;
		qcom,supply-name = "gdsc";
		qcom,supply-min-voltage = <0>;
		qcom,supply-max-voltage = <0>;
		qcom,supply-enable-load = <0>;
		qcom,supply-disable-load = <0>;
		};
		};

		qcom,ctrl-supply-entries {
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,ctrl-supply-entry@0 {
		reg = <0>;
		qcom,supply-name = "vdda-1p2";
		qcom,supply-min-voltage = <1200000>;
		qcom,supply-max-voltage = <1250000>;
		qcom,supply-enable-load = <12560>;
		qcom,supply-disable-load = <4>;
		};
		};

		qcom,phy-supply-entries {
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,phy-supply-entry@0 {
		reg = <0>;
		qcom,supply-name = "vdda-0p9";
		qcom,supply-min-voltage = <880000>;
		qcom,supply-max-voltage = <925000>;
		qcom,supply-enable-load = <73400>;
		qcom,supply-disable-load = <32>;
		};
		};
		};

		mdss_rotator: qcom,mdss_rotator {
		compatible = "qcom,sde_rotator";
		reg = <0x0c900000 0xab100>,
		<0x0c9b0000 0x1040>;
		reg-names = "mdp_phys",
		"rot_vbif_phys";

		qcom,mdss-rot-mode = <1>;
		qcom,mdss-highest-bank-bit = <0x1>;

		/* Bus Scale Settings */
		qcom,msm-bus,name = "mdss_rotator";
		qcom,msm-bus,num-cases = <3>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<22 512 0 0>,
		<22 512 0 6400000>,
		<22 512 0 6400000>;

		rot-vdd-supply = <&gdsc_mdss>;
		qcom,supply-names = "rot-vdd";

		clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>,
		<&clock_mmss MMSS_MDSS_AHB_CLK>,
		<&clock_mmss ROT_CLK_SRC>,
		<&clock_mmss MMSS_MDSS_ROT_CLK>,
		<&clock_mmss MMSS_MDSS_AXI_CLK>;
		clock-names = "mnoc_clk",
		"iface_clk", "rot_core_clk",
		"rot_clk", "axi_clk";

		interrupt-parent = <&mdss_mdp>;
		interrupts = <2 0>;

		/* VBIF QoS remapper settings*/
		qcom,mdss-rot-vbif-qos-setting = <1 1 1 1>;
		qcom,mdss-rot-xin-id = <14 15>;

		qcom,mdss-default-ot-rd-limit = <32>;
		qcom,mdss-default-ot-wr-limit = <40>;
		};
		};

		#include "sdm630-mdss-panels.dtsi"