Loading drivers/gpu/drm/msm/adreno/a5xx_gpu.c +8 −6 Original line number Diff line number Diff line Loading @@ -125,7 +125,8 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) struct msm_ringbuffer *ring = gpu->rb[submit->ring]; unsigned int i, ibs = 0; unsigned long flags; u64 ktime, ticks; u64 ticks; ktime_t time; a5xx_set_pagetable(gpu, ring, submit->aspace); Loading Loading @@ -253,18 +254,19 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) local_irq_save(flags); ticks = gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO, REG_A5XX_RBBM_ALWAYSON_COUNTER_HI); ktime = ktime_get_raw_ns(); time = ktime_get_raw(); local_irq_restore(flags); if (submit->profile_buf) { /* Write the data into the use-specified profile buffer */ struct timespec64 ts = ktime_to_timespec64(time); submit->profile_buf->queue_time = ktime; submit->profile_buf->submit_time = ktime; /* Write the data into the user-specified profile buffer */ submit->profile_buf->time.tv_sec = ts.tv_sec; submit->profile_buf->time.tv_nsec = ts.tv_nsec; submit->profile_buf->ticks_queued = ticks; } trace_msm_submitted(submit, ticks, ktime); trace_msm_submitted(submit, ticks, ktime_to_ns(time)); a5xx_flush(gpu, ring); Loading drivers/gpu/drm/msm/adreno/adreno_gpu.c +3 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,9 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) if (adreno_gpu->funcs->get_timestamp) return adreno_gpu->funcs->get_timestamp(gpu, value); return -EINVAL; case MSM_PARAM_NR_RINGS: *value = gpu->nr_rings; return 0; default: DBG("%s: invalid param: %u", gpu->name, param); return -EINVAL; Loading include/uapi/drm/msm_drm.h +9 −2 Original line number Diff line number Diff line Loading @@ -103,6 +103,7 @@ struct drm_msm_ext_panel_hdr_properties { #define MSM_PARAM_MAX_FREQ 0x04 #define MSM_PARAM_TIMESTAMP 0x05 #define MSM_PARAM_GMEM_BASE 0x06 #define MSM_PARAM_NR_RINGS 0x07 struct drm_msm_param { __u32 pipe; /* in, MSM_PIPE_x */ Loading Loading @@ -264,9 +265,15 @@ struct drm_msm_gem_submit { __u32 queueid; /* in, submitqueue id */ }; /* * Define a preprocessor variable to let the userspace know that * drm_msm_gem_submit_profile_buffer switched to only support a kernel timestamp * for submit time */ #define MSM_PROFILE_BUFFER_SUBMIT_TIME 1 struct drm_msm_gem_submit_profile_buffer { __s64 queue_time; /* out, Ringbuffer queue time (nsecs) */ __s64 submit_time; /* out, Ringbuffer submission time (nsecs) */ struct drm_msm_timespec time; /* out, submission time */ __u64 ticks_queued; /* out, GPU ticks at ringbuffer submission */ __u64 ticks_submitted; /* out, GPU ticks before cmdstream execution*/ __u64 ticks_retired; /* out, GPU ticks after cmdstream execution */ Loading Loading
drivers/gpu/drm/msm/adreno/a5xx_gpu.c +8 −6 Original line number Diff line number Diff line Loading @@ -125,7 +125,8 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) struct msm_ringbuffer *ring = gpu->rb[submit->ring]; unsigned int i, ibs = 0; unsigned long flags; u64 ktime, ticks; u64 ticks; ktime_t time; a5xx_set_pagetable(gpu, ring, submit->aspace); Loading Loading @@ -253,18 +254,19 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) local_irq_save(flags); ticks = gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO, REG_A5XX_RBBM_ALWAYSON_COUNTER_HI); ktime = ktime_get_raw_ns(); time = ktime_get_raw(); local_irq_restore(flags); if (submit->profile_buf) { /* Write the data into the use-specified profile buffer */ struct timespec64 ts = ktime_to_timespec64(time); submit->profile_buf->queue_time = ktime; submit->profile_buf->submit_time = ktime; /* Write the data into the user-specified profile buffer */ submit->profile_buf->time.tv_sec = ts.tv_sec; submit->profile_buf->time.tv_nsec = ts.tv_nsec; submit->profile_buf->ticks_queued = ticks; } trace_msm_submitted(submit, ticks, ktime); trace_msm_submitted(submit, ticks, ktime_to_ns(time)); a5xx_flush(gpu, ring); Loading
drivers/gpu/drm/msm/adreno/adreno_gpu.c +3 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,9 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) if (adreno_gpu->funcs->get_timestamp) return adreno_gpu->funcs->get_timestamp(gpu, value); return -EINVAL; case MSM_PARAM_NR_RINGS: *value = gpu->nr_rings; return 0; default: DBG("%s: invalid param: %u", gpu->name, param); return -EINVAL; Loading
include/uapi/drm/msm_drm.h +9 −2 Original line number Diff line number Diff line Loading @@ -103,6 +103,7 @@ struct drm_msm_ext_panel_hdr_properties { #define MSM_PARAM_MAX_FREQ 0x04 #define MSM_PARAM_TIMESTAMP 0x05 #define MSM_PARAM_GMEM_BASE 0x06 #define MSM_PARAM_NR_RINGS 0x07 struct drm_msm_param { __u32 pipe; /* in, MSM_PIPE_x */ Loading Loading @@ -264,9 +265,15 @@ struct drm_msm_gem_submit { __u32 queueid; /* in, submitqueue id */ }; /* * Define a preprocessor variable to let the userspace know that * drm_msm_gem_submit_profile_buffer switched to only support a kernel timestamp * for submit time */ #define MSM_PROFILE_BUFFER_SUBMIT_TIME 1 struct drm_msm_gem_submit_profile_buffer { __s64 queue_time; /* out, Ringbuffer queue time (nsecs) */ __s64 submit_time; /* out, Ringbuffer submission time (nsecs) */ struct drm_msm_timespec time; /* out, submission time */ __u64 ticks_queued; /* out, GPU ticks at ringbuffer submission */ __u64 ticks_submitted; /* out, GPU ticks before cmdstream execution*/ __u64 ticks_retired; /* out, GPU ticks after cmdstream execution */ Loading