Promotion of kernel.lnx.4.4-160620. (a83ca103) · Commits · e / devices / android_kernel_sony_msm8998

Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt

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		@@ -21,10 +21,17 @@ PROPERTIES
		the register region. An optional second element specifies
		the base address and size of the alias register region.

		- clock-output-names:
		Usage: optional
		Value type: <string>
		Definition: Name of the output clock. Typically acpuX_aux where X is a
		CPU number starting at 0.

		Example:

		clock-controller@2088000 {
		compatible = "qcom,kpss-acc-v2";
		reg = <0x02088000 0x1000>,
		<0x02008000 0x1000>;
		clock-output-names = "acpu0_aux";
		};

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		Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)

		PROPERTIES

		- compatible:
		Usage: required
		Value type: <string>
		Definition: should be one of:
		"qcom,kpss-gcc"

		- reg:
		Usage: required
		Value type: <prop-encoded-array>
		Definition: base address and size of the register region

		- clock-output-names:
		Usage: required
		Value type: <string>
		Definition: Name of the output clock. Typically acpu_l2_aux indicating
		an L2 cache auxiliary clock.

		Example:

		l2cc: clock-controller@2011000 {
		compatible = "qcom,kpss-gcc";
		reg = <0x2011000 0x1000>;
		clock-output-names = "acpu_l2_aux";
		};

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		High-Frequency PLL (HFPLL)

		PROPERTIES

		- compatible:
		Usage: required
		Value type: <string>
		Definition: must be "qcom,hfpll"

		- reg:
		Usage: required
		Value type: <prop-encoded-array>
		Definition: address and size of HPLL registers. An optional second
		element specifies the address and size of the alias
		register region.

		- clock-output-names:
		Usage: required
		Value type: <string>
		Definition: Name of the PLL. Typically hfpllX where X is a CPU number
		starting at 0. Otherwise hfpll_Y where Y is more specific
		such as "l2".

		Example:

		1) An HFPLL for the L2 cache.

		clock-controller@f9016000 {
		compatible = "qcom,hfpll";
		reg = <0xf9016000 0x30>;
		clock-output-names = "hfpll_l2";
		};

		2) An HFPLL for CPU0. This HFPLL has the alias register region.

		clock-controller@f908a000 {
		compatible = "qcom,hfpll";
		reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
		clock-output-names = "hfpll0";
		};

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		@@ -9,6 +9,7 @@ Required properties :
		"qcom,mmcc-msm8660"
		"qcom,mmcc-msm8960"
		"qcom,mmcc-msm8974"
		"qcom,mmcc-msm8996"

		- reg : shall contain base register location and length
		- #clock-cells : shall contain 1

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		@@ -125,6 +125,28 @@ Optional properties:
		"lane_map_1032" = <1 0 3 2>
		"lane_map_2103" = <2 1 0 3>
		"lane_map_3210" = <3 2 1 0>
		where lane_map_ABCD means:
		Logical_Lane_A = Physical_Lane_0
		Logical_Lane_B = Physical_Lane_1
		Logical_Lane_C = Physical_Lane_2
		Logical_Lane_D = Physical_Lane_3
		The lane map can vary between multiple instances
		of the DSI controller and should be set accordingly in all
		of them based on the board configuration.
		- qcom,lane-map-v2: An array of size 4 uint8s specifying the corresponding
		mapping for each of the logical data lanes.
		For example, a value of <A B C D> means
		Logical_Lane_0 = Physical_Lane_A
		Logical_Lane_1 = Physical_Lane_B
		Logical_Lane_2 = Physical_Lane_C
		Logical_Lane_3 = Physical_Lane_D
		The default lane mapping is <0 1 2 3>.
		Since the values are of type uint8, they need to be
		specified as below:
		qcom,lane-map-v2 = /bits/ 8 <0 1 2 3>
		This binding supersedes qcom,lane-map binding and will
		override any lane swap setting specified by qcom,lane-map.
		Refer to qcom,lane-map for additional notes.
		- qcom,pluggable Boolean to enable hotplug feature.
		- qcom,timing-db-mode: Boolean specifies dsi timing mode registers are supported or not.
		- qcom,display-id A string indicates the display ID for the controller.