Commit a81cbd2d authored Mar 04, 2009 by Oskar Schirmer Committed by Chris Zankel Apr 02, 2009

xtensa: enforce slab alignment to maximum register width



XCHAL_DATA_WIDTH is the maximum register width, slab caches should be
aligned to this.

Theoretical fix as all variants have had an XCHAL_DATA_WIDTH of 4
(wordsize) for now.  But the S6000 variant will raise this to 16.

Signed-off-by: Oskar Schirmer <os@emlix.com>
Signed-off-by: Johannes Weiner <jw@emlix.com>
Signed-off-by: Chris Zankel <chris@zankel.net>

parent c947a585

arch/xtensa/include/asm/processor.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -25,6 +25,8 @@
		# error Linux requires the Xtensa Windowed Registers Option.
		#endif

		#define ARCH_SLAB_MINALIGN XCHAL_DATA_WIDTH

		/*
		* User space process size: 1 GB.
		* Windowed call ABI requires caller and callee to be located within the same