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Commit a6fff3c8 authored by Linux Build Service Account's avatar Linux Build Service Account
Browse files

Promotion of kernel.lnx.4.4-161126. 

CRs      Change ID                                   Subject
--------------------------------------------------------------------------------------------------------------
1086894   I78770eea7fdd57f12d92ff40ed8043987e742024   msm: mdss: refine the calculation of tmds clock rate
1086976   Iae12fa648df17dddd48f3a71e94d06c2c3b03277   soc: qcom: socinfo: Change offset of image OEM attribute
1056661   If225dc4ec2c2e3eb8996f49f4fdf6acd31a50680   Revert "msm: kgsl: Enable limits management on A540v2"
1093546   I8f1cba6e1efa65ae41e674b14bd7598b4b521f05   soc: qcom: msm_bus: Set current index to default value
1092875   I53f89cf6b7c11f32c5e8e5a51a5986fa31424b92   qpnp-smb2: force UFP mode before shutdown
1084600   I53cd6ed709263669edbc34f096a21cddffcf4489   smb-lib: fix null ptr access while handling src change i
1081033   I6fc8323cbcf395a2c24e49e65cc7012709d031a2   input: synaptics_dsx: add checks of user input data
1086894   Ia3ea67cc7658098928a442460198b2dccc8ff8e1   msm: mdss: update vic info when powering on HDMI
1091972   I36ca125143cf9929fb0bd781990bdd8ab1dbeebf   ARM: dts: msm: Add thermal mitigation properties to msmf
1091972   Ie564c181db61f6229479a49917cdb9e6c1887fc5   ARM: dts: msm: Add thermal sensor info for msmfalcon
1091566   Ic68cd12cc861d04e107b70e2b96200483f13da26   qpnp-smb2: add support to configure auto recharge
1072067   I7c6ab8bc0e88010eb221788cf8ce4c182e3128d9   ASoc: msm: qdsp6v2: Add support for compress capture
1060631   Icb48ac2624d489ff054dca3158f52c45cc85cce7   msm: camera: Enable secure camera feature
1087473   I09fbda8eb92c81acf24d0ff07ca9c040141680e1   msm: mdss: fix to handle multi-rect configuration in err
1082636   I3db0c20ac5fa47ed278f3d60368c406f472430c1   msm: crypto: fix issues on digest buf and copy_from_user
1090500   Ie592d06d2e09c2e263a2e9485a42eafb368e49cc   include: clock: Add audio external clock of_index extrie
1084152   I48b5fc1c9e98994c8a7d92d462138cbacb246005   ASoC: wcd9335: Add dapm ignore suspend for codec dai

Change-Id: I0cc98bd7e0978cccd6a24fd1ead5e80d66e76a30
CRs-Fixed: 1056661, 1086894, 1087473, 1081033, 1091566, 1086976, 1093546, 1092875, 1060631, 1072067, 1084152, 1084600, 1090500, 1091972, 1082636
parents 9811ea8f b23cd82d

Documentation/devicetree/bindings/power/qcom-charger/qpnp-smb2.txt

+8 −0
Original line number Diff line number Diff line
@@ -138,6 +138,14 @@ Charger specific properties: 
		then charge inhibit will be disabled by default.

		Allowed values are: 50, 100, 200, 300.



- qcom,auto-recharge-soc

  Usage:      optional

  Value type: <empty>

  Definition: Specifies if automatic recharge needs to be based off battery

		SOC. If this property is not specified, then auto recharge will

		be based off battery voltage. For both SOC and battery voltage,

		charger receives the signal from FG to resume charging.



=============================================

Second Level Nodes - SMB2 Charger Peripherals

=============================================

arch/arm/boot/dts/qcom/msmfalcon.dtsi

+182 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";

			qcom,limits-info = <&mitigation_profile0>;

		};



		CPU1: cpu@1 {
@@ -54,6 +55,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x1>;

			enable-method = "psci";

			qcom,limits-info = <&mitigation_profile0>;

		};



		CPU2: cpu@2 {
@@ -61,6 +63,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x2>;

			enable-method = "psci";

			qcom,limits-info = <&mitigation_profile0>;

		};



		CPU3: cpu@3 {
@@ -68,6 +71,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x3>;

			enable-method = "psci";

			qcom,limits-info = <&mitigation_profile0>;

		};



		CPU4: cpu@100 {
@@ -75,6 +79,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

			qcom,limits-info = <&mitigation_profile1>;

		};



		CPU5: cpu@101 {
@@ -82,6 +87,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x101>;

			enable-method = "psci";

			qcom,limits-info = <&mitigation_profile2>;

		};



		CPU6: cpu@102 {
@@ -89,6 +95,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x102>;

			enable-method = "psci";

			qcom,limits-info = <&mitigation_profile3>;

		};



		CPU7: cpu@103 {
@@ -96,6 +103,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x103>;

			enable-method = "psci";

			qcom,limits-info = <&mitigation_profile4>;

		};



		cpu-map {
@@ -358,6 +366,180 @@ 
		clock-names = "core", "iface";

	};



	qcom,sensor-information {

		compatible = "qcom,sensor-information";

		sensor_information0: qcom,sensor-information-0 {

			qcom,sensor-type = "tsens";

			qcom,sensor-name = "tsens_tz_sensor0";

			qcom,scaling-factor = <10>;

		};

		sensor_information1: qcom,sensor-information-1 {

			qcom,sensor-type =  "tsens";

			qcom,sensor-name = "tsens_tz_sensor1";

			qcom,scaling-factor = <10>;

		};

		sensor_information2: qcom,sensor-information-2 {

			qcom,sensor-type =  "tsens";

			qcom,sensor-name = "tsens_tz_sensor2";

			qcom,scaling-factor = <10>;

		};

		sensor_information3: qcom,sensor-information-3 {

			qcom,sensor-type =  "tsens";

			qcom,sensor-name = "tsens_tz_sensor3";

			qcom,scaling-factor = <10>;

		};

		sensor_information4: qcom,sensor-information-4 {

			qcom,sensor-type = "tsens";

			qcom,sensor-name = "tsens_tz_sensor4";

			qcom,scaling-factor = <10>;

		};

		sensor_information5: qcom,sensor-information-5 {

			qcom,sensor-type = "tsens";

			qcom,sensor-name = "tsens_tz_sensor5";

			qcom,scaling-factor = <10>;

		};

		sensor_information6: qcom,sensor-information-6 {

			qcom,sensor-type = "tsens";

			qcom,sensor-name = "tsens_tz_sensor6";

			qcom,scaling-factor = <10>;

		};

		sensor_information7: qcom,sensor-information-7 {

			qcom,sensor-type = "tsens";

			qcom,sensor-name = "tsens_tz_sensor7";

			qcom,scaling-factor = <10>;

		};

		sensor_information8: qcom,sensor-information-8 {

			qcom,sensor-type = "tsens";

			qcom,sensor-name = "tsens_tz_sensor8";

			qcom,scaling-factor = <10>;

			qcom,alias-name = "gpu";

		};

		sensor_information9: qcom,sensor-information-9 {

			qcom,sensor-type = "tsens";

			qcom,sensor-name = "tsens_tz_sensor9";

			qcom,scaling-factor = <10>;

		};

		sensor_information10: qcom,sensor-information-10 {

			qcom,sensor-type = "tsens";

			qcom,sensor-name = "tsens_tz_sensor10";

			qcom,scaling-factor = <10>;

		};

		sensor_information11: qcom,sensor-information-11 {

			qcom,sensor-type = "tsens";

			qcom,sensor-name = "tsens_tz_sensor11";

			qcom,scaling-factor = <10>;

		};

		sensor_information12: qcom,sensor-information-12 {

			qcom,sensor-type = "tsens";

			qcom,sensor-name = "tsens_tz_sensor12";

			qcom,scaling-factor = <10>;

		};

		sensor_information13: qcom,sensor-information-13 {

			qcom,sensor-type = "tsens";

			qcom,sensor-name = "tsens_tz_sensor13";

			qcom,scaling-factor = <10>;

		};

		sensor_information14: qcom,sensor-information-14 {

			qcom,sensor-type =  "alarm";

			qcom,sensor-name = "pmfalcon_tz";

			qcom,scaling-factor = <1000>;

		};

		sensor_information15: qcom,sensor-information-15 {

			qcom,sensor-type =  "adc";

			qcom,sensor-name = "msm_therm";

		};

		sensor_information16: qcom,sensor-information-16 {

			qcom,sensor-type =  "adc";

			qcom,sensor-name = "xo_therm";

		};

		sensor_information17: qcom,sensor-information-17 {

			qcom,sensor-type =  "adc";

			qcom,sensor-name = "pa_therm0";

		};

		sensor_information18: qcom,sensor-information-18 {

			qcom,sensor-type =  "adc";

			qcom,sensor-name = "pa_therm1";

		};

		sensor_information19: qcom,sensor-information-19 {

			qcom,sensor-type =  "adc";

			qcom,sensor-name = "quiet_therm";

		};

		sensor_information20: qcom,sensor-information-20 {

			qcom,sensor-type = "llm";

			qcom,sensor-name = "limits_sensor-00";

		};

		sensor_information21: qcom,sensor-information-21 {

			qcom,sensor-type = "llm";

			qcom,sensor-name = "limits_sensor-01";

		};

	};



	mitigation_profile0: qcom,limit_info-0 {

		qcom,temperature-sensor = <&sensor_information1>;

		qcom,hotplug-mitigation-enable;

	};



	mitigation_profile1: qcom,limit_info-1 {

		qcom,temperature-sensor = <&sensor_information3>;

		qcom,hotplug-mitigation-enable;

	};



	mitigation_profile2: qcom,limit_info-2 {

		qcom,temperature-sensor = <&sensor_information4>;

		qcom,hotplug-mitigation-enable;

	};



	mitigation_profile3: qcom,limit_info-3 {

		qcom,temperature-sensor = <&sensor_information5>;

		qcom,hotplug-mitigation-enable;

	};



	mitigation_profile4: qcom,limit_info-4 {

		qcom,temperature-sensor = <&sensor_information6>;

		qcom,hotplug-mitigation-enable;

	};



	qcom,msm-thermal {

		compatible = "qcom,msm-thermal";

		qcom,sensor-id = <1>;

		qcom,poll-ms = <100>;

		qcom,therm-reset-temp = <115>;

		qcom,core-limit-temp = <70>;

		qcom,core-temp-hysteresis = <10>;

		qcom,hotplug-temp = <105>;

		qcom,hotplug-temp-hysteresis = <20>;

		qcom,online-hotplug-core;

		qcom,synchronous-cluster-id = <0 1>;

		qcom,synchronous-cluster-map = <0 4 &CPU0 &CPU1 &CPU2 &CPU3>,

						<1 4 &CPU4 &CPU5 &CPU6 &CPU7>;



		qcom,vdd-restriction-temp = <5>;

		qcom,vdd-restriction-temp-hysteresis = <10>;



		vdd-dig-supply = <&pm2falcon_s3_floor_level>;

		vdd-gfx-supply = <&gfx_vreg_corner>;



		qcom,vdd-dig-rstr{

			qcom,vdd-rstr-reg = "vdd-dig";

			qcom,levels = <RPM_SMD_REGULATOR_LEVEL_NOM

					RPM_SMD_REGULATOR_LEVEL_TURBO

					RPM_SMD_REGULATOR_LEVEL_TURBO>;

			qcom,min-level = <RPM_SMD_REGULATOR_LEVEL_NONE>;

		};



		qcom,vdd-gfx-rstr{

			qcom,vdd-rstr-reg = "vdd-gfx";

			qcom,levels = <5 6 6>; /* Nominal, Turbo, Turbo */

			qcom,min-level = <1>; /* No Request */

		};



		msm_thermal_freq: qcom,vdd-apps-rstr{

			qcom,vdd-rstr-reg = "vdd-apps";

			qcom,levels = <1248000>;

			qcom,freq-req;

		};

	};



	uartblsp2dm1: serial@0c1b0000 {

		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

		reg = <0xc1b0000 0x1000>;

drivers/crypto/msm/qcedev.c

+27 −93
Original line number Diff line number Diff line
@@ -603,7 +603,7 @@ static int qcedev_sha_update_max_xfer(struct qcedev_async_req *qcedev_areq, 
		while (len > 0) {

			user_src =

			(void __user *)qcedev_areq->sha_op_req.data[i].vaddr;

			if (user_src && __copy_from_user(k_src,

			if (user_src && copy_from_user(k_src,

				(void __user *)user_src,

				qcedev_areq->sha_op_req.data[i].len))

				return -EFAULT;
@@ -639,7 +639,7 @@ static int qcedev_sha_update_max_xfer(struct qcedev_async_req *qcedev_areq, 


	/* Copy data from user src(s) */

	user_src = (void __user *)qcedev_areq->sha_op_req.data[0].vaddr;

	if (user_src && __copy_from_user(k_src,

	if (user_src && copy_from_user(k_src,

				(void __user *)user_src,

				qcedev_areq->sha_op_req.data[0].len)) {

		kzfree(k_buf_src);
@@ -648,7 +648,7 @@ static int qcedev_sha_update_max_xfer(struct qcedev_async_req *qcedev_areq, 
	k_src += qcedev_areq->sha_op_req.data[0].len;

	for (i = 1; i < qcedev_areq->sha_op_req.entries; i++) {

		user_src = (void __user *)qcedev_areq->sha_op_req.data[i].vaddr;

		if (user_src && __copy_from_user(k_src,

		if (user_src && copy_from_user(k_src,

					(void __user *)user_src,

					qcedev_areq->sha_op_req.data[i].len)) {

			kzfree(k_buf_src);
@@ -702,13 +702,6 @@ static int qcedev_sha_update(struct qcedev_async_req *qcedev_areq, 
		return -EINVAL;

	}



	/* verify address src(s) */

	for (i = 0; i < qcedev_areq->sha_op_req.entries; i++)

		if (!access_ok(VERIFY_READ,

			(void __user *)qcedev_areq->sha_op_req.data[i].vaddr,

			qcedev_areq->sha_op_req.data[i].len))

			return -EFAULT;



	if (qcedev_areq->sha_op_req.data_len > QCE_MAX_OPER_DATA) {



		struct	qcedev_sha_op_req *saved_req;
@@ -868,19 +861,7 @@ static int qcedev_hash_cmac(struct qcedev_async_req *qcedev_areq, 


	total = qcedev_areq->sha_op_req.data_len;



	/* verify address src(s) */

	for (i = 0; i < qcedev_areq->sha_op_req.entries; i++)

		if (!access_ok(VERIFY_READ,

			(void __user *)qcedev_areq->sha_op_req.data[i].vaddr,

			qcedev_areq->sha_op_req.data[i].len))

			return -EFAULT;



	/* Verify Source Address */

	if (!access_ok(VERIFY_READ,

				(void __user *)qcedev_areq->sha_op_req.authkey,

				qcedev_areq->sha_op_req.authklen))

			return -EFAULT;

	if (__copy_from_user(&handle->sha_ctxt.authkey[0],

	if (copy_from_user(&handle->sha_ctxt.authkey[0],

				(void __user *)qcedev_areq->sha_op_req.authkey,

				qcedev_areq->sha_op_req.authklen))

		return -EFAULT;
@@ -900,7 +881,7 @@ static int qcedev_hash_cmac(struct qcedev_async_req *qcedev_areq, 
	for (i = 0; i < qcedev_areq->sha_op_req.entries; i++) {

		user_src =

			(void __user *)qcedev_areq->sha_op_req.data[i].vaddr;

		if (user_src && __copy_from_user(k_src, (void __user *)user_src,

		if (user_src && copy_from_user(k_src, (void __user *)user_src,

				qcedev_areq->sha_op_req.data[i].len)) {

			kzfree(k_buf_src);

			return -EFAULT;
@@ -928,12 +909,7 @@ static int qcedev_set_hmac_auth_key(struct qcedev_async_req *areq, 


	if (areq->sha_op_req.authklen <= QCEDEV_MAX_KEY_SIZE) {

		qcedev_sha_init(areq, handle);

		/* Verify Source Address */

		if (!access_ok(VERIFY_READ,

				(void __user *)areq->sha_op_req.authkey,

				areq->sha_op_req.authklen))

			return -EFAULT;

		if (__copy_from_user(&handle->sha_ctxt.authkey[0],

		if (copy_from_user(&handle->sha_ctxt.authkey[0],

				(void __user *)areq->sha_op_req.authkey,

				areq->sha_op_req.authklen))

			return -EFAULT;
@@ -1146,7 +1122,7 @@ static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq, 
		byteoffset = areq->cipher_op_req.byteoffset;



	user_src = (void __user *)areq->cipher_op_req.vbuf.src[0].vaddr;

	if (user_src && __copy_from_user((k_align_src + byteoffset),

	if (user_src && copy_from_user((k_align_src + byteoffset),

				(void __user *)user_src,

				areq->cipher_op_req.vbuf.src[0].len))

		return -EFAULT;
@@ -1156,7 +1132,7 @@ static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq, 
	for (i = 1; i < areq->cipher_op_req.entries; i++) {

		user_src =

			(void __user *)areq->cipher_op_req.vbuf.src[i].vaddr;

		if (user_src && __copy_from_user(k_align_src,

		if (user_src && copy_from_user(k_align_src,

					(void __user *)user_src,

					areq->cipher_op_req.vbuf.src[i].len)) {

			return -EFAULT;
@@ -1188,7 +1164,7 @@ static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq, 


	while (creq->data_len > 0) {

		if (creq->vbuf.dst[dst_i].len <= creq->data_len) {

			if (err == 0 && __copy_to_user(

			if (err == 0 && copy_to_user(

				(void __user *)creq->vbuf.dst[dst_i].vaddr,

					(k_align_dst + byteoffset),

					creq->vbuf.dst[dst_i].len))
@@ -1199,7 +1175,7 @@ static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq, 
			creq->data_len -= creq->vbuf.dst[dst_i].len;

			dst_i++;

		} else {

				if (err == 0 && __copy_to_user(

				if (err == 0 && copy_to_user(

				(void __user *)creq->vbuf.dst[dst_i].vaddr,

				(k_align_dst + byteoffset),

				creq->data_len))
@@ -1531,36 +1507,6 @@ static int qcedev_check_cipher_params(struct qcedev_cipher_op_req *req, 
			__func__, total, req->data_len);

		goto error;

	}

	/* Verify Source Address's */

	for (i = 0, total = 0; i < req->entries; i++) {

		if (total < req->data_len) {

			if (!access_ok(VERIFY_READ,

				(void __user *)req->vbuf.src[i].vaddr,

				req->vbuf.src[i].len)) {

				pr_err("%s:SRC RD_VERIFY err %d=0x%lx\n",

					__func__, i, (uintptr_t)

					req->vbuf.src[i].vaddr);

				goto error;

			}

			total += req->vbuf.src[i].len;

		}

	}



	/* Verify Destination Address's */

	for (i = 0, total = 0; i < QCEDEV_MAX_BUFFERS; i++) {

		if ((req->vbuf.dst[i].vaddr != 0) &&

			(total < req->data_len)) {

			if (!access_ok(VERIFY_WRITE,

				(void __user *)req->vbuf.dst[i].vaddr,

				req->vbuf.dst[i].len)) {

				pr_err("%s:DST WR_VERIFY err %d=0x%lx\n",

					__func__, i, (uintptr_t)

					req->vbuf.dst[i].vaddr);

				goto error;

			}

			total += req->vbuf.dst[i].len;

		}

	}

	return 0;

error:

	return -EINVAL;
@@ -1656,11 +1602,7 @@ long qcedev_ioctl(struct file *file, unsigned cmd, unsigned long arg) 
	switch (cmd) {

	case QCEDEV_IOCTL_ENC_REQ:

	case QCEDEV_IOCTL_DEC_REQ:

		if (!access_ok(VERIFY_WRITE, (void __user *)arg,

				sizeof(struct qcedev_cipher_op_req)))

			return -EFAULT;



		if (__copy_from_user(&qcedev_areq.cipher_op_req,

		if (copy_from_user(&qcedev_areq.cipher_op_req,

				(void __user *)arg,

				sizeof(struct qcedev_cipher_op_req)))

			return -EFAULT;
@@ -1673,7 +1615,7 @@ long qcedev_ioctl(struct file *file, unsigned cmd, unsigned long arg) 
		err = qcedev_vbuf_ablk_cipher(&qcedev_areq, handle);

		if (err)

			return err;

		if (__copy_to_user((void __user *)arg,

		if (copy_to_user((void __user *)arg,

					&qcedev_areq.cipher_op_req,

					sizeof(struct qcedev_cipher_op_req)))

			return -EFAULT;
@@ -1682,11 +1624,8 @@ long qcedev_ioctl(struct file *file, unsigned cmd, unsigned long arg) 
	case QCEDEV_IOCTL_SHA_INIT_REQ:

		{

		struct scatterlist sg_src;

		if (!access_ok(VERIFY_WRITE, (void __user *)arg,

				sizeof(struct qcedev_sha_op_req)))

			return -EFAULT;



		if (__copy_from_user(&qcedev_areq.sha_op_req,

		if (copy_from_user(&qcedev_areq.sha_op_req,

					(void __user *)arg,

					sizeof(struct qcedev_sha_op_req)))

			return -EFAULT;
@@ -1696,7 +1635,7 @@ long qcedev_ioctl(struct file *file, unsigned cmd, unsigned long arg) 
		err = qcedev_hash_init(&qcedev_areq, handle, &sg_src);

		if (err)

			return err;

		if (__copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,

		if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,

					sizeof(struct qcedev_sha_op_req)))

			return -EFAULT;

		}
@@ -1708,11 +1647,8 @@ long qcedev_ioctl(struct file *file, unsigned cmd, unsigned long arg) 
	case QCEDEV_IOCTL_SHA_UPDATE_REQ:

		{

		struct scatterlist sg_src;

		if (!access_ok(VERIFY_WRITE, (void __user *)arg,

				sizeof(struct qcedev_sha_op_req)))

			return -EFAULT;



		if (__copy_from_user(&qcedev_areq.sha_op_req,

		if (copy_from_user(&qcedev_areq.sha_op_req,

					(void __user *)arg,

					sizeof(struct qcedev_sha_op_req)))

			return -EFAULT;
@@ -1734,10 +1670,15 @@ long qcedev_ioctl(struct file *file, unsigned cmd, unsigned long arg) 
				return err;

		}



		if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {

			pr_err("Invalid sha_ctxt.diglen %d\n",

					handle->sha_ctxt.diglen);

			return -EINVAL;

		}

		memcpy(&qcedev_areq.sha_op_req.digest[0],

				&handle->sha_ctxt.digest[0],

				handle->sha_ctxt.diglen);

		if (__copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,

		if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,

					sizeof(struct qcedev_sha_op_req)))

			return -EFAULT;

		}
@@ -1749,11 +1690,7 @@ long qcedev_ioctl(struct file *file, unsigned cmd, unsigned long arg) 
			pr_err("%s Init was not called\n", __func__);

			return -EINVAL;

		}

		if (!access_ok(VERIFY_WRITE, (void __user *)arg,

				sizeof(struct qcedev_sha_op_req)))

			return -EFAULT;



		if (__copy_from_user(&qcedev_areq.sha_op_req,

		if (copy_from_user(&qcedev_areq.sha_op_req,

					(void __user *)arg,

					sizeof(struct qcedev_sha_op_req)))

			return -EFAULT;
@@ -1767,7 +1704,7 @@ long qcedev_ioctl(struct file *file, unsigned cmd, unsigned long arg) 
		memcpy(&qcedev_areq.sha_op_req.digest[0],

				&handle->sha_ctxt.digest[0],

				handle->sha_ctxt.diglen);

		if (__copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,

		if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,

					sizeof(struct qcedev_sha_op_req)))

			return -EFAULT;

		handle->sha_ctxt.init_done = false;
@@ -1776,11 +1713,8 @@ long qcedev_ioctl(struct file *file, unsigned cmd, unsigned long arg) 
	case QCEDEV_IOCTL_GET_SHA_REQ:

		{

		struct scatterlist sg_src;

		if (!access_ok(VERIFY_WRITE, (void __user *)arg,

				sizeof(struct qcedev_sha_op_req)))

			return -EFAULT;



		if (__copy_from_user(&qcedev_areq.sha_op_req,

		if (copy_from_user(&qcedev_areq.sha_op_req,

					(void __user *)arg,

					sizeof(struct qcedev_sha_op_req)))

			return -EFAULT;
@@ -1798,7 +1732,7 @@ long qcedev_ioctl(struct file *file, unsigned cmd, unsigned long arg) 
		memcpy(&qcedev_areq.sha_op_req.digest[0],

				&handle->sha_ctxt.digest[0],

				handle->sha_ctxt.diglen);

		if (__copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,

		if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,

					sizeof(struct qcedev_sha_op_req)))

			return -EFAULT;

		}

drivers/gpu/msm/adreno-gpulist.h

+1 −1
Original line number Diff line number Diff line
@@ -269,7 +269,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.patchid = ANY_ID,

		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION |

			ADRENO_GPMU | ADRENO_SPTP_PC | ADRENO_LM,

			ADRENO_GPMU | ADRENO_SPTP_PC,

		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a540_zap",

drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_fw_update.c

+7 −0
Original line number Diff line number Diff line
@@ -1606,6 +1606,13 @@ static ssize_t fwu_sysfs_store_image(struct file *data_file, 
		struct kobject *kobj, struct bin_attribute *attributes,

		char *buf, loff_t pos, size_t count)

{

	if (count > (fwu->image_size - fwu->data_pos)) {

		dev_err(fwu->rmi4_data->pdev->dev.parent,

				"%s: Not enough space in buffer\n",

				__func__);

		return -EINVAL;

	}



	memcpy((void *)(&fwu->ext_data_source[fwu->data_pos]),

			(const void *)buf,

			count);