Commit a67004a3 authored Mar 29, 2017 by Frederic Barrat Committed by Greg Kroah-Hartman Apr 12, 2017

powerpc/mm: Add missing global TLB invalidate if cxl is active



commit 88b1bf7268f56887ca88eb09c6fb0f4fc970121a upstream.

Commit 4c6d9acc ("powerpc/mm: Add hooks for cxl") converted local
TLB invalidates to global if the cxl driver is active. This is necessary
because the CAPP snoops invalidations to forward them to the PSL on the
cxl adapter. However one path was forgotten. native_flush_hash_range()
still does local TLB invalidates, as found out the hard way recently.

This patch fixes it by following the same logic as previously: if the
cxl driver is active, the local TLB invalidates are 'upgraded' to
global.

Fixes: 4c6d9acc ("powerpc/mm: Add hooks for cxl")
Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent 435cc436

arch/powerpc/mm/hash_native_64.c

+5 −2

Original line number	Diff line number	Diff line
		@@ -645,6 +645,10 @@ static void native_flush_hash_range(unsigned long number, int local)
		unsigned long psize = batch->psize;
		int ssize = batch->ssize;
		int i;
		unsigned int use_local;

		use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) &&
		mmu_psize_defs[psize].tlbiel && !cxl_ctx_in_use();

		local_irq_save(flags);

		@@ -671,8 +675,7 @@ static void native_flush_hash_range(unsigned long number, int local)
		} pte_iterate_hashed_end();
		}

		if (mmu_has_feature(MMU_FTR_TLBIEL) &&
		mmu_psize_defs[psize].tlbiel && local) {
		if (use_local) {
		asm volatile("ptesync":::"memory");
		for (i = 0; i < number; i++) {
		vpn = batch->vpn[i];