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Commit a4d443b7 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.4.202 into android-4.4-p 



Changes in 4.4.202
	kvm: mmu: Don't read PDPTEs when paging is not enabled
	MIPS: BCM63XX: fix switch core reset on BCM6368
	powerpc/Makefile: Use cflags-y/aflags-y for setting endian options
	powerpc: Fix compiling a BE kernel with a powerpc64le toolchain
	powerpc/boot: Request no dynamic linker for boot wrapper
	KVM: Introduce kvm_get_arch_capabilities()
	KVM: x86: Emulate MSR_IA32_ARCH_CAPABILITIES on AMD hosts
	kvm: x86: IA32_ARCH_CAPABILITIES is always supported
	KVM: x86: use Intel speculation bugs and features as derived in generic x86 code
	x86/msr: Add the IA32_TSX_CTRL MSR
	x86/cpu: Add a helper function x86_read_arch_cap_msr()
	x86/cpu: Add a "tsx=" cmdline option with TSX disabled by default
	x86/speculation/taa: Add mitigation for TSX Async Abort
	x86/speculation/taa: Add sysfs reporting for TSX Async Abort
	kvm/x86: Export MDS_NO=0 to guests when TSX is enabled
	x86/tsx: Add "auto" option to the tsx= cmdline parameter
	x86/speculation/taa: Add documentation for TSX Async Abort
	x86/tsx: Add config options to set tsx=on|off|auto
	x86/speculation/taa: Fix printing of TAA_MSG_SMT on IBRS_ALL CPUs
	x86/bugs: Add ITLB_MULTIHIT bug infrastructure
	Linux 4.4.202

Change-Id: I0c8187a61060810c9a2e56c09ba17768939de271
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
parents ef0b39d3 bc69c961

Documentation/ABI/testing/sysfs-devices-system-cpu

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@@ -279,6 +279,8 @@ What: /sys/devices/system/cpu/vulnerabilities 
		/sys/devices/system/cpu/vulnerabilities/spec_store_bypass

		/sys/devices/system/cpu/vulnerabilities/l1tf

		/sys/devices/system/cpu/vulnerabilities/mds

		/sys/devices/system/cpu/vulnerabilities/tsx_async_abort

		/sys/devices/system/cpu/vulnerabilities/itlb_multihit

Date:		January 2018

Contact:	Linux kernel mailing list <linux-kernel@vger.kernel.org>

Description:	Information about CPU vulnerabilities

Documentation/hw-vuln/tsx_async_abort.rst

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.. SPDX-License-Identifier: GPL-2.0



TAA - TSX Asynchronous Abort

======================================



TAA is a hardware vulnerability that allows unprivileged speculative access to

data which is available in various CPU internal buffers by using asynchronous

aborts within an Intel TSX transactional region.



Affected processors

-------------------



This vulnerability only affects Intel processors that support Intel

Transactional Synchronization Extensions (TSX) when the TAA_NO bit (bit 8)

is 0 in the IA32_ARCH_CAPABILITIES MSR.  On processors where the MDS_NO bit

(bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations

also mitigate against TAA.



Whether a processor is affected or not can be read out from the TAA

vulnerability file in sysfs. See :ref:`tsx_async_abort_sys_info`.



Related CVEs

------------



The following CVE entry is related to this TAA issue:



   ==============  =====  ===================================================

   CVE-2019-11135  TAA    TSX Asynchronous Abort (TAA) condition on some

                          microprocessors utilizing speculative execution may

                          allow an authenticated user to potentially enable

                          information disclosure via a side channel with

                          local access.

   ==============  =====  ===================================================



Problem

-------



When performing store, load or L1 refill operations, processors write

data into temporary microarchitectural structures (buffers). The data in

those buffers can be forwarded to load operations as an optimization.



Intel TSX is an extension to the x86 instruction set architecture that adds

hardware transactional memory support to improve performance of multi-threaded

software. TSX lets the processor expose and exploit concurrency hidden in an

application due to dynamically avoiding unnecessary synchronization.



TSX supports atomic memory transactions that are either committed (success) or

aborted. During an abort, operations that happened within the transactional region

are rolled back. An asynchronous abort takes place, among other options, when a

different thread accesses a cache line that is also used within the transactional

region when that access might lead to a data race.



Immediately after an uncompleted asynchronous abort, certain speculatively

executed loads may read data from those internal buffers and pass it to dependent

operations. This can be then used to infer the value via a cache side channel

attack.



Because the buffers are potentially shared between Hyper-Threads cross

Hyper-Thread attacks are possible.



The victim of a malicious actor does not need to make use of TSX. Only the

attacker needs to begin a TSX transaction and raise an asynchronous abort

which in turn potenitally leaks data stored in the buffers.



More detailed technical information is available in the TAA specific x86

architecture section: :ref:`Documentation/x86/tsx_async_abort.rst <tsx_async_abort>`.





Attack scenarios

----------------



Attacks against the TAA vulnerability can be implemented from unprivileged

applications running on hosts or guests.



As for MDS, the attacker has no control over the memory addresses that can

be leaked. Only the victim is responsible for bringing data to the CPU. As

a result, the malicious actor has to sample as much data as possible and

then postprocess it to try to infer any useful information from it.



A potential attacker only has read access to the data. Also, there is no direct

privilege escalation by using this technique.





.. _tsx_async_abort_sys_info:



TAA system information

-----------------------



The Linux kernel provides a sysfs interface to enumerate the current TAA status

of mitigated systems. The relevant sysfs file is:



/sys/devices/system/cpu/vulnerabilities/tsx_async_abort



The possible values in this file are:



.. list-table::



   * - 'Vulnerable'

     - The CPU is affected by this vulnerability and the microcode and kernel mitigation are not applied.

   * - 'Vulnerable: Clear CPU buffers attempted, no microcode'

     - The system tries to clear the buffers but the microcode might not support the operation.

   * - 'Mitigation: Clear CPU buffers'

     - The microcode has been updated to clear the buffers. TSX is still enabled.

   * - 'Mitigation: TSX disabled'

     - TSX is disabled.

   * - 'Not affected'

     - The CPU is not affected by this issue.



.. _ucode_needed:



Best effort mitigation mode

^^^^^^^^^^^^^^^^^^^^^^^^^^^



If the processor is vulnerable, but the availability of the microcode-based

mitigation mechanism is not advertised via CPUID the kernel selects a best

effort mitigation mode.  This mode invokes the mitigation instructions

without a guarantee that they clear the CPU buffers.



This is done to address virtualization scenarios where the host has the

microcode update applied, but the hypervisor is not yet updated to expose the

CPUID to the guest. If the host has updated microcode the protection takes

effect; otherwise a few CPU cycles are wasted pointlessly.



The state in the tsx_async_abort sysfs file reflects this situation

accordingly.





Mitigation mechanism

--------------------



The kernel detects the affected CPUs and the presence of the microcode which is

required. If a CPU is affected and the microcode is available, then the kernel

enables the mitigation by default.





The mitigation can be controlled at boot time via a kernel command line option.

See :ref:`taa_mitigation_control_command_line`.



.. _virt_mechanism:



Virtualization mitigation

^^^^^^^^^^^^^^^^^^^^^^^^^



Affected systems where the host has TAA microcode and TAA is mitigated by

having disabled TSX previously, are not vulnerable regardless of the status

of the VMs.



In all other cases, if the host either does not have the TAA microcode or

the kernel is not mitigated, the system might be vulnerable.





.. _taa_mitigation_control_command_line:



Mitigation control on the kernel command line

---------------------------------------------



The kernel command line allows to control the TAA mitigations at boot time with

the option "tsx_async_abort=". The valid arguments for this option are:



  ============  =============================================================

  off		This option disables the TAA mitigation on affected platforms.

                If the system has TSX enabled (see next parameter) and the CPU

                is affected, the system is vulnerable.



  full	        TAA mitigation is enabled. If TSX is enabled, on an affected

                system it will clear CPU buffers on ring transitions. On

                systems which are MDS-affected and deploy MDS mitigation,

                TAA is also mitigated. Specifying this option on those

                systems will have no effect.

  ============  =============================================================



Not specifying this option is equivalent to "tsx_async_abort=full".



The kernel command line also allows to control the TSX feature using the

parameter "tsx=" on CPUs which support TSX control. MSR_IA32_TSX_CTRL is used

to control the TSX feature and the enumeration of the TSX feature bits (RTM

and HLE) in CPUID.



The valid options are:



  ============  =============================================================

  off		Disables TSX on the system.



                Note that this option takes effect only on newer CPUs which are

                not vulnerable to MDS, i.e., have MSR_IA32_ARCH_CAPABILITIES.MDS_NO=1

                and which get the new IA32_TSX_CTRL MSR through a microcode

                update. This new MSR allows for the reliable deactivation of

                the TSX functionality.



  on		Enables TSX.



                Although there are mitigations for all known security

                vulnerabilities, TSX has been known to be an accelerator for

                several previous speculation-related CVEs, and so there may be

                unknown security risks associated with leaving it enabled.



  auto		Disables TSX if X86_BUG_TAA is present, otherwise enables TSX

                on the system.

  ============  =============================================================



Not specifying this option is equivalent to "tsx=off".



The following combinations of the "tsx_async_abort" and "tsx" are possible. For

affected platforms tsx=auto is equivalent to tsx=off and the result will be:



  =========  ==========================   =========================================

  tsx=on     tsx_async_abort=full         The system will use VERW to clear CPU

                                          buffers. Cross-thread attacks are still

					  possible on SMT machines.

  tsx=on     tsx_async_abort=off          The system is vulnerable.

  tsx=off    tsx_async_abort=full         TSX might be disabled if microcode

                                          provides a TSX control MSR. If so,

					  system is not vulnerable.

  tsx=off    tsx_async_abort=off          ditto

  =========  ==========================   =========================================





For unaffected platforms "tsx=on" and "tsx_async_abort=full" does not clear CPU

buffers.  For platforms without TSX control (MSR_IA32_ARCH_CAPABILITIES.MDS_NO=0)

"tsx" command line argument has no effect.



For the affected platforms below table indicates the mitigation status for the

combinations of CPUID bit MD_CLEAR and IA32_ARCH_CAPABILITIES MSR bits MDS_NO

and TSX_CTRL_MSR.



  =======  =========  =============  ========================================

  MDS_NO   MD_CLEAR   TSX_CTRL_MSR   Status

  =======  =========  =============  ========================================

    0          0            0        Vulnerable (needs microcode)

    0          1            0        MDS and TAA mitigated via VERW

    1          1            0        MDS fixed, TAA vulnerable if TSX enabled

                                     because MD_CLEAR has no meaning and

                                     VERW is not guaranteed to clear buffers

    1          X            1        MDS fixed, TAA can be mitigated by

                                     VERW or TSX_CTRL_MSR

  =======  =========  =============  ========================================



Mitigation selection guide

--------------------------



1. Trusted userspace and guests

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^



If all user space applications are from a trusted source and do not execute

untrusted code which is supplied externally, then the mitigation can be

disabled. The same applies to virtualized environments with trusted guests.





2. Untrusted userspace and guests

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^



If there are untrusted applications or guests on the system, enabling TSX

might allow a malicious actor to leak data from the host or from other

processes running on the same physical core.



If the microcode is available and the TSX is disabled on the host, attacks

are prevented in a virtualized environment as well, even if the VMs do not

explicitly enable the mitigation.





.. _taa_default_mitigations:



Default mitigations

-------------------



The kernel's default action for vulnerable processors is:



  - Deploy TSX disable mitigation (tsx_async_abort=full tsx=off).

Documentation/kernel-parameters.txt

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@@ -2230,6 +2230,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted. 
					       spectre_v2_user=off [X86]

					       spec_store_bypass_disable=off [X86]

					       mds=off [X86]

					       tsx_async_abort=off [X86]



			auto (default)

				Mitigate all CPU vulnerabilities, but leave SMT
@@ -4116,6 +4117,67 @@ bytes respectively. Such letter suffixes can also be entirely omitted. 
			platforms where RDTSC is slow and this accounting

			can add overhead.



	tsx=		[X86] Control Transactional Synchronization

			Extensions (TSX) feature in Intel processors that

			support TSX control.



			This parameter controls the TSX feature. The options are:



			on	- Enable TSX on the system. Although there are

				mitigations for all known security vulnerabilities,

				TSX has been known to be an accelerator for

				several previous speculation-related CVEs, and

				so there may be unknown	security risks associated

				with leaving it enabled.



			off	- Disable TSX on the system. (Note that this

				option takes effect only on newer CPUs which are

				not vulnerable to MDS, i.e., have

				MSR_IA32_ARCH_CAPABILITIES.MDS_NO=1 and which get

				the new IA32_TSX_CTRL MSR through a microcode

				update. This new MSR allows for the reliable

				deactivation of the TSX functionality.)



			auto	- Disable TSX if X86_BUG_TAA is present,

				  otherwise enable TSX on the system.



			Not specifying this option is equivalent to tsx=off.



			See Documentation/hw-vuln/tsx_async_abort.rst

			for more details.



	tsx_async_abort= [X86,INTEL] Control mitigation for the TSX Async

			Abort (TAA) vulnerability.



			Similar to Micro-architectural Data Sampling (MDS)

			certain CPUs that support Transactional

			Synchronization Extensions (TSX) are vulnerable to an

			exploit against CPU internal buffers which can forward

			information to a disclosure gadget under certain

			conditions.



			In vulnerable processors, the speculatively forwarded

			data can be used in a cache side channel attack, to

			access data to which the attacker does not have direct

			access.



			This parameter controls the TAA mitigation.  The

			options are:



			full       - Enable TAA mitigation on vulnerable CPUs

				     if TSX is enabled.



			off        - Unconditionally disable TAA mitigation



			Not specifying this option is equivalent to

			tsx_async_abort=full.  On CPUs which are MDS affected

			and deploy MDS mitigation, TAA mitigation is not

			required and doesn't provide any additional

			mitigation.



			For details see:

			Documentation/hw-vuln/tsx_async_abort.rst



	turbografx.map[2|3]=	[HW,JOY]

			TurboGraFX parallel port interface

			Format:

Documentation/x86/tsx_async_abort.rst

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.. SPDX-License-Identifier: GPL-2.0



TSX Async Abort (TAA) mitigation

================================



.. _tsx_async_abort:



Overview

--------



TSX Async Abort (TAA) is a side channel attack on internal buffers in some

Intel processors similar to Microachitectural Data Sampling (MDS).  In this

case certain loads may speculatively pass invalid data to dependent operations

when an asynchronous abort condition is pending in a Transactional

Synchronization Extensions (TSX) transaction.  This includes loads with no

fault or assist condition. Such loads may speculatively expose stale data from

the same uarch data structures as in MDS, with same scope of exposure i.e.

same-thread and cross-thread. This issue affects all current processors that

support TSX.



Mitigation strategy

-------------------



a) TSX disable - one of the mitigations is to disable TSX. A new MSR

IA32_TSX_CTRL will be available in future and current processors after

microcode update which can be used to disable TSX. In addition, it

controls the enumeration of the TSX feature bits (RTM and HLE) in CPUID.



b) Clear CPU buffers - similar to MDS, clearing the CPU buffers mitigates this

vulnerability. More details on this approach can be found in

:ref:`Documentation/hw-vuln/mds.rst <mds>`.



Kernel internal mitigation modes

--------------------------------



 =============    ============================================================

 off              Mitigation is disabled. Either the CPU is not affected or

                  tsx_async_abort=off is supplied on the kernel command line.



 tsx disabled     Mitigation is enabled. TSX feature is disabled by default at

                  bootup on processors that support TSX control.



 verw             Mitigation is enabled. CPU is affected and MD_CLEAR is

                  advertised in CPUID.



 ucode needed     Mitigation is enabled. CPU is affected and MD_CLEAR is not

                  advertised in CPUID. That is mainly for virtualization

                  scenarios where the host has the updated microcode but the

                  hypervisor does not expose MD_CLEAR in CPUID. It's a best

                  effort approach without guarantee.

 =============    ============================================================



If the CPU is affected and the "tsx_async_abort" kernel command line parameter is

not provided then the kernel selects an appropriate mitigation depending on the

status of RTM and MD_CLEAR CPUID bits.



Below tables indicate the impact of tsx=on|off|auto cmdline options on state of

TAA mitigation, VERW behavior and TSX feature for various combinations of

MSR_IA32_ARCH_CAPABILITIES bits.



1. "tsx=off"



=========  =========  ============  ============  ==============  ===================  ======================

MSR_IA32_ARCH_CAPABILITIES bits     Result with cmdline tsx=off

----------------------------------  -------------------------------------------------------------------------

TAA_NO     MDS_NO     TSX_CTRL_MSR  TSX state     VERW can clear  TAA mitigation       TAA mitigation

                                    after bootup  CPU buffers     tsx_async_abort=off  tsx_async_abort=full

=========  =========  ============  ============  ==============  ===================  ======================

    0          0           0         HW default         Yes           Same as MDS           Same as MDS

    0          0           1        Invalid case   Invalid case       Invalid case          Invalid case

    0          1           0         HW default         No         Need ucode update     Need ucode update

    0          1           1          Disabled          Yes           TSX disabled          TSX disabled

    1          X           1          Disabled           X             None needed           None needed

=========  =========  ============  ============  ==============  ===================  ======================



2. "tsx=on"



=========  =========  ============  ============  ==============  ===================  ======================

MSR_IA32_ARCH_CAPABILITIES bits     Result with cmdline tsx=on

----------------------------------  -------------------------------------------------------------------------

TAA_NO     MDS_NO     TSX_CTRL_MSR  TSX state     VERW can clear  TAA mitigation       TAA mitigation

                                    after bootup  CPU buffers     tsx_async_abort=off  tsx_async_abort=full

=========  =========  ============  ============  ==============  ===================  ======================

    0          0           0         HW default        Yes            Same as MDS          Same as MDS

    0          0           1        Invalid case   Invalid case       Invalid case         Invalid case

    0          1           0         HW default        No          Need ucode update     Need ucode update

    0          1           1          Enabled          Yes               None              Same as MDS

    1          X           1          Enabled          X              None needed          None needed

=========  =========  ============  ============  ==============  ===================  ======================



3. "tsx=auto"



=========  =========  ============  ============  ==============  ===================  ======================

MSR_IA32_ARCH_CAPABILITIES bits     Result with cmdline tsx=auto

----------------------------------  -------------------------------------------------------------------------

TAA_NO     MDS_NO     TSX_CTRL_MSR  TSX state     VERW can clear  TAA mitigation       TAA mitigation

                                    after bootup  CPU buffers     tsx_async_abort=off  tsx_async_abort=full

=========  =========  ============  ============  ==============  ===================  ======================

    0          0           0         HW default    Yes                Same as MDS           Same as MDS

    0          0           1        Invalid case  Invalid case        Invalid case          Invalid case

    0          1           0         HW default    No              Need ucode update     Need ucode update

    0          1           1          Disabled      Yes               TSX disabled          TSX disabled

    1          X           1          Enabled       X                 None needed           None needed

=========  =========  ============  ============  ==============  ===================  ======================



In the tables, TSX_CTRL_MSR is a new bit in MSR_IA32_ARCH_CAPABILITIES that

indicates whether MSR_IA32_TSX_CTRL is supported.



There are two control bits in IA32_TSX_CTRL MSR:



      Bit 0: When set it disables the Restricted Transactional Memory (RTM)

             sub-feature of TSX (will force all transactions to abort on the

             XBEGIN instruction).



      Bit 1: When set it disables the enumeration of the RTM and HLE feature

             (i.e. it will make CPUID(EAX=7).EBX{bit4} and

             CPUID(EAX=7).EBX{bit11} read as 0).

Makefile

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VERSION = 4

PATCHLEVEL = 4

SUBLEVEL = 201

SUBLEVEL = 202

EXTRAVERSION =

NAME = Blurry Fish Butt