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Commit a4ca7944 authored by Tirupathi Reddy's avatar Tirupathi Reddy
Browse files

ARM: dts: msm: Enable ACD functionality for sdm630 CPU rails 



The adaptive clock distribution (ACD) mitigates the impact of
high-frequency supply voltage (VDD) droops on microprocessor
performance. Program ACD functional configuration for both
Silver and Gold clusters of sdm630.

Also set VCTL_RAMP_EN & VCTL_RAMP_EN to 1 in SAW4_AVS_CTL.

CRs-Fixed: 2074210
Change-Id: I1f8021b8b436602b22a87d2036aebbfcf6840f58
Signed-off-by: default avatarTirupathi Reddy <tirupath@codeaurora.org>
parent d6f171ce

arch/arm/boot/dts/qcom/sdm630-pm.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ 
		qcom,vctl-timeout-us = <500>;

		qcom,vctl-port = <0x0>;

		qcom,phase-port = <0x1>;

		qcom,saw2-avs-ctl = <0x1010031>;

		qcom,saw2-avs-ctl = <0x101c031>;

		qcom,saw2-avs-limit = <0x4580458>;

		qcom,pfm-port = <0x2>;

	};
@@ -40,7 +40,7 @@ 
		qcom,vctl-timeout-us = <500>;

		qcom,vctl-port = <0x0>;

		qcom,phase-port = <0x1>;

		qcom,saw2-avs-ctl = <0x1010031>;

		qcom,saw2-avs-ctl = <0x101c031>;

		qcom,saw2-avs-limit = <0x4580458>;

		qcom,pfm-port = <0x2>;

	};

arch/arm/boot/dts/qcom/sdm630.dtsi

+11 −2
Original line number Diff line number Diff line
@@ -1292,9 +1292,18 @@ 
		compatible = "qcom,clk-cpu-osm-sdm630";

		reg = <0x179c0000 0x4000>, <0x17916000 0x1000>,

			<0x17816000 0x1000>, <0x179d1000 0x1000>,

			<0x00784130 0x8>;

			<0x00784130 0x8>, <0x17914800 0x800>,

			<0x17814800 0x800>;

		reg-names = "osm", "pwrcl_pll", "perfcl_pll",

			"apcs_common", "perfcl_efuse";

			"apcs_common", "perfcl_efuse",

			"pwrcl_acd", "perfcl_acd";



		qcom,acdtd-val = <0x0000a111 0x0000a111>;

		qcom,acdcr-val = <0x002c5ffd 0x002c5ffd>;

		qcom,acdsscr-val = <0x00000901 0x00000901>;

		qcom,acdextint0-val = <0x2cf9ae8 0x2cf9ae8>;

		qcom,acdextint1-val = <0x2cf9afe 0x2cf9afe>;

		qcom,acdautoxfer-val = <0x00000015 0x00000015>;



		vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;

		vdd-perfcl-supply = <&apc1_perfcl_vreg>;