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Commit a443a637 authored by Thomas Abraham's avatar Thomas Abraham Committed by Ben Dooks
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ARM: S5PC100: Pre-requisite clock patch for plat-s5pc1xx to plat-s5p move 



This is a pre-requisite clock patch for the plat-s5pc1xx to plat-s5p
movement. The patches that perform the movement of the code from
plat-s5pc1xx to plat-s5p (and mach-s5pc100) should also enable the
build for the mach-s5pc100/clock.c code.

Signed-off-by: default avatarThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
parent a0f73581

arch/arm/mach-s5pc100/clock.c

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+1358 −0

File added.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-s5pc100/include/mach/regs-clock.h

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/* linux/arch/arm/mach-s5pc100/include/mach/regs-clock.h

 *

 * Copyright (c) 2010 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com/

 *

 * S5PC100 - Clock register definitions

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

*/



#ifndef __ASM_ARCH_REGS_CLOCK_H

#define __ASM_ARCH_REGS_CLOCK_H __FILE__



#include <mach/map.h>



#define S5P_CLKREG(x)		(S3C_VA_SYS + (x))



#define S5P_APLL_LOCK		S5P_CLKREG(0x00)

#define S5P_MPLL_LOCK		S5P_CLKREG(0x04)

#define S5P_EPLL_LOCK		S5P_CLKREG(0x08)

#define S5P_HPLL_LOCK		S5P_CLKREG(0x0C)



#define S5P_APLL_CON		S5P_CLKREG(0x100)

#define S5P_MPLL_CON		S5P_CLKREG(0x104)

#define S5P_EPLL_CON		S5P_CLKREG(0x108)

#define S5P_HPLL_CON		S5P_CLKREG(0x10C)



#define S5P_CLK_SRC0		S5P_CLKREG(0x200)

#define S5P_CLK_SRC1		S5P_CLKREG(0x204)

#define S5P_CLK_SRC2		S5P_CLKREG(0x208)

#define S5P_CLK_SRC3		S5P_CLKREG(0x20C)



#define S5P_CLK_DIV0		S5P_CLKREG(0x300)

#define S5P_CLK_DIV1		S5P_CLKREG(0x304)

#define S5P_CLK_DIV2		S5P_CLKREG(0x308)

#define S5P_CLK_DIV3		S5P_CLKREG(0x30C)

#define S5P_CLK_DIV4		S5P_CLKREG(0x310)



#define S5P_CLK_OUT		S5P_CLKREG(0x400)



#define S5P_CLKGATE_D00		S5P_CLKREG(0x500)

#define S5P_CLKGATE_D01		S5P_CLKREG(0x504)

#define S5P_CLKGATE_D02		S5P_CLKREG(0x508)



#define S5P_CLKGATE_D10		S5P_CLKREG(0x520)

#define S5P_CLKGATE_D11		S5P_CLKREG(0x524)

#define S5P_CLKGATE_D12		S5P_CLKREG(0x528)

#define S5P_CLKGATE_D13		S5P_CLKREG(0x52C)

#define S5P_CLKGATE_D14		S5P_CLKREG(0x530)

#define S5P_CLKGATE_D15		S5P_CLKREG(0x534)



#define S5P_CLKGATE_D20		S5P_CLKREG(0x540)



#define S5P_CLKGATE_SCLK0	S5P_CLKREG(0x560)

#define S5P_CLKGATE_SCLK1	S5P_CLKREG(0x564)



/* CLKDIV0 */

#define S5P_CLKDIV0_D0_MASK		(0x7<<8)

#define S5P_CLKDIV0_D0_SHIFT		(8)

#define S5P_CLKDIV0_PCLKD0_MASK		(0x7<<12)

#define S5P_CLKDIV0_PCLKD0_SHIFT	(12)



/* CLKDIV1 */

#define S5P_CLKDIV1_D1_MASK		(0x7<<12)

#define S5P_CLKDIV1_D1_SHIFT		(12)

#define S5P_CLKDIV1_PCLKD1_MASK		(0x7<<16)

#define S5P_CLKDIV1_PCLKD1_SHIFT	(16)



#endif /* __ASM_ARCH_REGS_CLOCK_H */

arch/arm/plat-s5p/clock.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -38,7 +38,7 @@ struct clk clk_xusbxti = { 
	.id		= -1,

	.id		= -1,

};

};





static struct clk s5p_clk_27m = {

struct clk s5p_clk_27m = {

	.name		= "clk_27m",

	.name		= "clk_27m",

	.id		= -1,

	.id		= -1,

	.rate		= 27000000,

	.rate		= 27000000,

arch/arm/plat-s5p/include/plat/pll.h

+22 −0
Original line number Original line Diff line number Diff line
@@ -81,3 +81,25 @@ static inline unsigned long s5p_get_pll90xx(unsigned long baseclk, 




	return result;

	return result;

}

}



#define PLL65XX_MDIV_MASK	(0x3FF)

#define PLL65XX_PDIV_MASK	(0x3F)

#define PLL65XX_SDIV_MASK	(0x7)

#define PLL65XX_MDIV_SHIFT	(16)

#define PLL65XX_PDIV_SHIFT	(8)

#define PLL65XX_SDIV_SHIFT	(0)



static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con)

{

	u32 mdiv, pdiv, sdiv;

	u64 fvco = baseclk;



	mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;

	pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;

	sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;



	fvco *= mdiv;

	do_div(fvco, (pdiv << sdiv));



	return (unsigned long)fvco;

}

arch/arm/plat-s5p/include/plat/s5p-clock.h

+2 −0
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@@ -21,10 +21,12 @@ 
#define clk_fin_mpll clk_ext_xtal_mux

#define clk_fin_mpll clk_ext_xtal_mux

#define clk_fin_epll clk_ext_xtal_mux

#define clk_fin_epll clk_ext_xtal_mux

#define clk_fin_vpll clk_ext_xtal_mux

#define clk_fin_vpll clk_ext_xtal_mux

#define clk_fin_hpll clk_ext_xtal_mux





extern struct clk clk_ext_xtal_mux;

extern struct clk clk_ext_xtal_mux;

extern struct clk clk_xusbxti;

extern struct clk clk_xusbxti;

extern struct clk clk_48m;

extern struct clk clk_48m;

extern struct clk s5p_clk_27m;

extern struct clk clk_fout_apll;

extern struct clk clk_fout_apll;

extern struct clk clk_fout_mpll;

extern struct clk clk_fout_mpll;

extern struct clk clk_fout_epll;

extern struct clk clk_fout_epll;