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Commit a2821146 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'vexpress/timer' into next/timer 

* vexpress/timer:
  ARM: versatile: Map local timers using Device Tree when possible
  ARM: vexpress: Get rid of MMIO_P2V
parents 69adb983 e129440a

arch/arm/include/asm/hardware/arm_timer.h

+5 −0
Original line number Diff line number Diff line
@@ -9,7 +9,12 @@ 
 *

 * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview

 * can have 16-bit or 32-bit selectable via a bit in the control register.

 *

 * Every SP804 contains two identical timers.

 */

#define TIMER_1_BASE	0x00

#define TIMER_2_BASE	0x20



#define TIMER_LOAD	0x00			/* ACVR rw */

#define TIMER_VALUE	0x04			/* ACVR ro */

#define TIMER_CTRL	0x08			/* ACVR rw */

arch/arm/mach-vexpress/core.h

+6 −3
Original line number Diff line number Diff line 
#define __MMIO_P2V(x)	(((x) & 0xfffff) | (((x) & 0x0f000000) >> 4) | 0xf8000000)

#define MMIO_P2V(x)	((void __iomem *)__MMIO_P2V(x))



#define AMBA_DEVICE(name,busid,base,plat)	\

struct amba_device name##_device = {		\

	.dev		= {			\
@@ -17,3 +14,9 @@ struct amba_device name##_device = { \ 
	.irq		= IRQ_##base,		\

	/* .dma		= DMA_##base,*/		\

}



/* 2MB large area for motherboard's peripherals static mapping */

#define V2M_PERIPH 0xf8000000



/* Tile's peripherals static mappings should start here */

#define V2T_PERIPH 0xf8200000

arch/arm/mach-vexpress/ct-ca9x4.c

+19 −39
Original line number Diff line number Diff line
@@ -30,57 +30,29 @@ 


#include <plat/clcd.h>



#define V2M_PA_CS7	0x10000000



static struct map_desc ct_ca9x4_io_desc[] __initdata = {

	{

		.virtual	= __MMIO_P2V(CT_CA9X4_MPIC),

		.virtual        = V2T_PERIPH,

		.pfn            = __phys_to_pfn(CT_CA9X4_MPIC),

		.length		= SZ_16K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= __MMIO_P2V(CT_CA9X4_SP804_TIMER),

		.pfn		= __phys_to_pfn(CT_CA9X4_SP804_TIMER),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= __MMIO_P2V(CT_CA9X4_L2CC),

		.pfn		= __phys_to_pfn(CT_CA9X4_L2CC),

		.length		= SZ_4K,

		.length         = SZ_8K,

		.type           = MT_DEVICE,

	},

};



static void __init ct_ca9x4_map_io(void)

{

	iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));

#ifdef CONFIG_LOCAL_TIMERS

	twd_base = MMIO_P2V(A9_MPCORE_TWD);

	twd_base = ioremap(A9_MPCORE_TWD, SZ_32);

#endif

	iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));

}



static void __init ct_ca9x4_init_irq(void)

{

	gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),

		 MMIO_P2V(A9_MPCORE_GIC_CPU));

	gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),

		 ioremap(A9_MPCORE_GIC_CPU, SZ_256));

}



#if 0

static void __init ct_ca9x4_timer_init(void)

{

	writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);

	writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);



	sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");

	sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,

		"ct-timer0");

}



static struct sys_timer ct_ca9x4_timer = {

	.init	= ct_ca9x4_timer_init,

};

#endif



static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)

{

	v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
@@ -201,7 +173,7 @@ static void __init ct_ca9x4_init(void) 
	int i;



#ifdef CONFIG_CACHE_L2X0

	void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);

	void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);



	/* set RAM latencies to 1 cycle for this core tile. */

	writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
@@ -217,9 +189,17 @@ static void __init ct_ca9x4_init(void) 
}



#ifdef CONFIG_SMP

static void *ct_ca9x4_scu_base __initdata;



static void __init ct_ca9x4_init_cpu_map(void)

{

	int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));

	int i, ncores;



	ct_ca9x4_scu_base = ioremap(A9_MPCORE_SCU, SZ_128);

	if (WARN_ON(!ct_ca9x4_scu_base))

		return;



	ncores = scu_get_core_count(ct_ca9x4_scu_base);



	if (ncores > nr_cpu_ids) {

		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
@@ -235,7 +215,7 @@ static void __init ct_ca9x4_init_cpu_map(void) 


static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)

{

	scu_enable(MMIO_P2V(A9_MPCORE_SCU));

	scu_enable(ct_ca9x4_scu_base);

}

#endif

arch/arm/mach-vexpress/include/mach/ct-ca9x4.h

+0 −3
Original line number Diff line number Diff line
@@ -22,9 +22,6 @@ 
#define CT_CA9X4_SYSWDT		(0x1e007000)

#define CT_CA9X4_L2CC		(0x1e00a000)



#define CT_CA9X4_TIMER0		(CT_CA9X4_SP804_TIMER + 0x000)

#define CT_CA9X4_TIMER1		(CT_CA9X4_SP804_TIMER + 0x020)



#define A9_MPCORE_SCU		(CT_CA9X4_MPIC + 0x0000)

#define A9_MPCORE_GIC_CPU	(CT_CA9X4_MPIC + 0x0100)

#define A9_MPCORE_GIT		(CT_CA9X4_MPIC + 0x0200)

arch/arm/mach-vexpress/include/mach/motherboard.h

+25 −27
Original line number Diff line number Diff line
@@ -39,33 +39,30 @@ 
#define V2M_CF			(V2M_PA_CS7 + 0x0001a000)

#define V2M_CLCD		(V2M_PA_CS7 + 0x0001f000)



#define V2M_SYS_ID		(V2M_SYSREGS + 0x000)

#define V2M_SYS_SW		(V2M_SYSREGS + 0x004)

#define V2M_SYS_LED		(V2M_SYSREGS + 0x008)

#define V2M_SYS_100HZ		(V2M_SYSREGS + 0x024)

#define V2M_SYS_FLAGS		(V2M_SYSREGS + 0x030)

#define V2M_SYS_FLAGSSET	(V2M_SYSREGS + 0x030)

#define V2M_SYS_FLAGSCLR	(V2M_SYSREGS + 0x034)

#define V2M_SYS_NVFLAGS		(V2M_SYSREGS + 0x038)

#define V2M_SYS_NVFLAGSSET	(V2M_SYSREGS + 0x038)

#define V2M_SYS_NVFLAGSCLR	(V2M_SYSREGS + 0x03c)

#define V2M_SYS_MCI		(V2M_SYSREGS + 0x048)

#define V2M_SYS_FLASH		(V2M_SYSREGS + 0x03c)

#define V2M_SYS_CFGSW		(V2M_SYSREGS + 0x058)

#define V2M_SYS_24MHZ		(V2M_SYSREGS + 0x05c)

#define V2M_SYS_MISC		(V2M_SYSREGS + 0x060)

#define V2M_SYS_DMA		(V2M_SYSREGS + 0x064)

#define V2M_SYS_PROCID0		(V2M_SYSREGS + 0x084)

#define V2M_SYS_PROCID1		(V2M_SYSREGS + 0x088)

#define V2M_SYS_CFGDATA		(V2M_SYSREGS + 0x0a0)

#define V2M_SYS_CFGCTRL		(V2M_SYSREGS + 0x0a4)

#define V2M_SYS_CFGSTAT		(V2M_SYSREGS + 0x0a8)



#define V2M_TIMER0		(V2M_TIMER01 + 0x000)

#define V2M_TIMER1		(V2M_TIMER01 + 0x020)



#define V2M_TIMER2		(V2M_TIMER23 + 0x000)

#define V2M_TIMER3		(V2M_TIMER23 + 0x020)

/*

 * Offsets from SYSREGS base

 */

#define V2M_SYS_ID		0x000

#define V2M_SYS_SW		0x004

#define V2M_SYS_LED		0x008

#define V2M_SYS_100HZ		0x024

#define V2M_SYS_FLAGS		0x030

#define V2M_SYS_FLAGSSET	0x030

#define V2M_SYS_FLAGSCLR	0x034

#define V2M_SYS_NVFLAGS		0x038

#define V2M_SYS_NVFLAGSSET	0x038

#define V2M_SYS_NVFLAGSCLR	0x03c

#define V2M_SYS_MCI		0x048

#define V2M_SYS_FLASH		0x03c

#define V2M_SYS_CFGSW		0x058

#define V2M_SYS_24MHZ		0x05c

#define V2M_SYS_MISC		0x060

#define V2M_SYS_DMA		0x064

#define V2M_SYS_PROCID0		0x084

#define V2M_SYS_PROCID1		0x088

#define V2M_SYS_CFGDATA		0x0a0

#define V2M_SYS_CFGCTRL		0x0a4

#define V2M_SYS_CFGSTAT		0x0a8





/*
@@ -117,6 +114,7 @@ 


int v2m_cfg_write(u32 devfn, u32 data);

int v2m_cfg_read(u32 devfn, u32 *data);

void v2m_flags_set(u32 data);



/*

 * Core tile IDs