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Commit a26ae43d authored by Osvaldo Banuelos's avatar Osvaldo Banuelos Committed by Kyle Yan
Browse files

ARM: dts: msm: add CPR panic register configuration for msmcobalt 



Specify the panic register configuration in the VDD_APC0
and VDD_APC1 CPR device nodes. This enables the CPR panic
handler to dump the values of the specified registers during
a kernel panic.

CRs-Fixed: 1033060
Change-Id: Ifdd03f27ed1135acd4470d891e1b5aca4a11dd65
Signed-off-by: default avatarOsvaldo Banuelos <osvaldob@codeaurora.org>
parent 506ddf3b

arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -614,6 +614,11 @@ 
		qcom,cpr-enable;

		qcom,cpr-hw-closed-loop;



		qcom,cpr-panic-reg-addr-list =

			<0x179cbaa4 0x17912c18>;

		qcom,cpr-panic-reg-name-list =

			"PWR_CPRH_STATUS", "APCLUS0_L2_SAW4_PMIC_STS";



		thread@0 {

			qcom,cpr-thread-id = <0>;

			qcom,cpr-consecutive-up = <0>;
@@ -770,6 +775,11 @@ 
		qcom,cpr-enable;

		qcom,cpr-hw-closed-loop;



		qcom,cpr-panic-reg-addr-list =

			<0x179c7aa4 0x17812c18>;

		qcom,cpr-panic-reg-name-list =

			"PERF_CPRH_STATUS", "APCLUS1_L2_SAW4_PMIC_STS";



		thread@0 {

			qcom,cpr-thread-id = <0>;

			qcom,cpr-consecutive-up = <0>;