Merge "clk: qcom: Add support to set rcg parent src for dp_pixel clock" (9f0ae8e6) · Commits · e / devices / android_kernel_sony_msm8998

drivers/clk/qcom/clk-rcg2.c

+13 −2

Original line number	Diff line number	Diff line
		@@ -1060,7 +1060,8 @@ static int clk_dp_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long src_rate;
		unsigned long num, den;
		u32 mask = BIT(rcg->hid_width) - 1;
		u32 hid_div;
		u32 hid_div, cfg;
		int i, num_parents = clk_hw_get_num_parents(hw);

		src_rate = clk_get_rate(clk_hw_get_parent(hw)->clk);
		if (src_rate <= 0) {
		@@ -1078,7 +1079,17 @@ static int clk_dp_set_rate(struct clk_hw *hw, unsigned long rate,
		return -EINVAL;
		}

		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &hid_div);
		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
		hid_div = cfg;
		cfg &= CFG_SRC_SEL_MASK;
		cfg >>= CFG_SRC_SEL_SHIFT;

		for (i = 0; i < num_parents; i++)
		if (cfg == rcg->parent_map[i].cfg) {
		f.src = rcg->parent_map[i].src;
		break;
		}

		f.pre_div = hid_div;
		f.pre_div >>= CFG_SRC_DIV_SHIFT;
		f.pre_div &= mask;