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Commit 9b87a506 authored by Tatenda Chipeperekwa's avatar Tatenda Chipeperekwa Committed by Gerrit - the friendly Code Review server
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msm: mdss: dp: update parsing of AUX controller configurations 



Make the parsing of the AUX controller configurations more
extensible by adding support for multiple settings per configuration,
as well as the parsing of the register offsets. This enables the
extension to support different targets, and combinations of AUX
controller settings depending on the use case.

CRs-Fixed: 2006096
Change-Id: I4e6b623a4d9fafcfcc89477dfa57880eb798c350
Signed-off-by: default avatarTatenda Chipeperekwa <tatendac@codeaurora.org>
parent 7d8800fa

Documentation/devicetree/bindings/fb/mdss-dp.txt

+50 −2
Original line number Diff line number Diff line
@@ -27,7 +27,46 @@ Required properties 
- qcom,aux-en-gpio:			Specifies the aux-channel enable gpio.

- qcom,aux-sel-gpio:			Specifies the aux-channel select gpio.

- qcom,usbplug-cc-gpio:			Specifies the usbplug orientation gpio.

- qcom,aux-cfg-settings:		An array that specifies the DP AUX configuration settings.

- qcom,aux-cfg0-settings:		Specifies the DP AUX configuration 0 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg1-settings:		Specifies the DP AUX configuration 1 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg2-settings:		Specifies the DP AUX configuration 2 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg3-settings:		Specifies the DP AUX configuration 3 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg4-settings:		Specifies the DP AUX configuration 4 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg5-settings:		Specifies the DP AUX configuration 5 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg6-settings:		Specifies the DP AUX configuration 6 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg7-settings:		Specifies the DP AUX configuration 7 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg8-settings:		Specifies the DP AUX configuration 8 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg9-settings:		Specifies the DP AUX configuration 9 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.



Optional properties:

- qcom,<type>-supply-entries:		A node that lists the elements of the supply used by the
@@ -87,7 +126,16 @@ Example: 
			"core_aux_clk", "core_cfg_ahb_clk", "ctrl_link_clk",

			"ctrl_link_iface_clk", "ctrl_crypto_clk", "ctrl_pixel_clk";



		qcom,aux-cfg-settings = [00 13 00 10 0a 26 0a 03 8b 03];

		qcom,aux-cfg0-settings = [1c 00];

		qcom,aux-cfg1-settings = [20 13 23 1d];

		qcom,aux-cfg2-settings = [24 00];

		qcom,aux-cfg3-settings = [28 00];

		qcom,aux-cfg4-settings = [2c 0a];

		qcom,aux-cfg5-settings = [30 26];

		qcom,aux-cfg6-settings = [34 0a];

		qcom,aux-cfg7-settings = [38 03];

		qcom,aux-cfg8-settings = [3c bb];

		qcom,aux-cfg9-settings = [40 03];

		qcom,logical2physical-lane-map = [02 03 01 00];

		qcom,phy-register-offset = <0x4>;

		qcom,max-pclk-frequency-khz = <593470>;

arch/arm/boot/dts/qcom/msm8998-mdss.dtsi

+10 −1
Original line number Diff line number Diff line
@@ -502,7 +502,16 @@ 


		qcom,msm_ext_disp = <&msm_ext_disp>;



		qcom,aux-cfg-settings = [00 13 00 10 0a 26 0a 03 8b 03];

		qcom,aux-cfg0-settings = [1c 00];

		qcom,aux-cfg1-settings = [20 13 23 1d];

		qcom,aux-cfg2-settings = [24 00];

		qcom,aux-cfg3-settings = [28 00];

		qcom,aux-cfg4-settings = [2c 0a];

		qcom,aux-cfg5-settings = [30 26];

		qcom,aux-cfg6-settings = [34 0a];

		qcom,aux-cfg7-settings = [38 03];

		qcom,aux-cfg8-settings = [3c bb];

		qcom,aux-cfg9-settings = [40 03];

		qcom,logical2physical-lane-map = [02 03 01 00];



		qcom,core-supply-entries {

arch/arm/boot/dts/qcom/sdm660-mdss.dtsi

+10 −1
Original line number Diff line number Diff line
@@ -505,7 +505,16 @@ 


		qcom,msm_ext_disp = <&msm_ext_disp>;



		qcom,aux-cfg-settings = [00 13 00 00 0a 28 0a 03 b7 03];

		qcom,aux-cfg0-settings = [20 00];

		qcom,aux-cfg1-settings = [24 13 23 1d];

		qcom,aux-cfg2-settings = [28 00];

		qcom,aux-cfg3-settings = [2c 00];

		qcom,aux-cfg4-settings = [30 0a];

		qcom,aux-cfg5-settings = [34 28];

		qcom,aux-cfg6-settings = [38 0a];

		qcom,aux-cfg7-settings = [3c 03];

		qcom,aux-cfg8-settings = [40 b7];

		qcom,aux-cfg9-settings = [44 03];

		qcom,logical2physical-lane-map = [00 01 02 03];

		qcom,phy-register-offset = <0x4>;

		qcom,max-pclk-frequency-khz = <300000>;

drivers/video/fbdev/msm/mdss_dp.c

+68 −12
Original line number Diff line number Diff line
@@ -138,22 +138,77 @@ static int mdss_dp_is_clk_prefix(const char *clk_prefix, const char *clk_name) 
	return !strncmp(clk_name, clk_prefix, strlen(clk_prefix));

}



static int mdss_dp_parse_prop(struct platform_device *pdev,

			struct mdss_dp_drv_pdata *dp_drv)

static void mdss_dp_reset_phy_config_indices(struct mdss_dp_drv_pdata *dp)

{

	int len = 0, i = 0, rc = 0;

	int i = 0;



	for (i = 0; i < PHY_AUX_CFG_MAX; i++)

		dp->aux_cfg[i].current_index = 0;

}



static void mdss_dp_phy_aux_cfg_reset(struct mdss_dp_drv_pdata *dp)

{

	int i = 0;



	for (i = 0; i < PHY_AUX_CFG_MAX; i++)

		dp->aux_cfg[i] = (const struct mdss_dp_phy_cfg){ 0 };

}



static int mdss_dp_parse_aux_cfg(struct platform_device *pdev,

			struct mdss_dp_drv_pdata *dp)

{

	int len = 0, i = 0, j = 0, config_count = 0;

	const char *data;

	int const minimum_config_count = 1;



	data = of_get_property(pdev->dev.of_node,

		"qcom,aux-cfg-settings", &len);

	if ((!data) || (len != AUX_CFG_LEN)) {

		pr_err("%s:%d, Unable to read DP AUX CFG settings",

			__func__, __LINE__);

	for (i = 0; i < PHY_AUX_CFG_MAX; i++) {

		const char *property = mdss_dp_get_phy_aux_config_property(i);



		data = of_get_property(pdev->dev.of_node, property, &len);

		if (!data) {

			pr_err("Unable to read %s\n", property);

			goto error;

		}



		config_count = len - 1;

		if ((config_count < minimum_config_count) ||

			(config_count > MDSS_DP_MAX_PHY_CFG_VALUE_CNT)) {

			pr_err("Invalid config count (%d) configs for %s\n",

					config_count, property);

			goto error;

		}



		dp->aux_cfg[i].offset = data[0];

		dp->aux_cfg[i].cfg_cnt = config_count;

		pr_debug("%s offset=0x%x, cfg_cnt=%d\n",

				property,

				dp->aux_cfg[i].offset,

				dp->aux_cfg[i].cfg_cnt);

		for (j = 1; j < len; j++) {

			dp->aux_cfg[i].lut[j - 1] = data[j];

			pr_debug("%s lut[%d]=0x%x\n",

					property,

					i,

					dp->aux_cfg[i].lut[j - 1]);

		}

	}



	return 0;



error:

	mdss_dp_phy_aux_cfg_reset(dp);

	return -EINVAL;

}



	for (i = 0; i < len; i++)

		dp_drv->aux_cfg[i] = data[i];

static int mdss_dp_parse_prop(struct platform_device *pdev,

			struct mdss_dp_drv_pdata *dp_drv)

{

	int len = 0, i = 0, rc = 0;

	const char *data;



	rc = mdss_dp_parse_aux_cfg(pdev, dp_drv);

	if (rc)

		return rc;



	data = of_get_property(pdev->dev.of_node,

		"qcom,logical2physical-lane-map", &len);
@@ -1908,14 +1963,15 @@ static int mdss_dp_host_init(struct mdss_panel_data *pdata) 
	mdss_dp_phy_reset(&dp_drv->ctrl_io);

	mdss_dp_aux_reset(&dp_drv->ctrl_io);

	mdss_dp_aux_set_limits(&dp_drv->ctrl_io);



	mdss_dp_aux_ctrl(&dp_drv->ctrl_io, true);



	pr_debug("Ctrl_hw_rev =0x%x, phy hw_rev =0x%x\n",

	       mdss_dp_get_ctrl_hw_version(&dp_drv->ctrl_io),

	       mdss_dp_get_phy_hw_version(&dp_drv->phy_io));



	mdss_dp_phy_aux_setup(&dp_drv->phy_io, dp_drv->aux_cfg,

			dp_drv->phy_reg_offset);

	mdss_dp_reset_phy_config_indices(dp_drv);

	mdss_dp_phy_aux_setup(dp_drv);



	mdss_dp_irq_enable(dp_drv);

	dp_drv->dp_initialized = true;

drivers/video/fbdev/msm/mdss_dp.h

+80 −1
Original line number Diff line number Diff line
@@ -429,6 +429,85 @@ struct mdss_dp_crc_data { 
	u32 b_cb;

};



#define MDSS_DP_MAX_PHY_CFG_VALUE_CNT 3

struct mdss_dp_phy_cfg {

	u32 cfg_cnt;

	u32 current_index;

	u32 offset;

	u32 lut[MDSS_DP_MAX_PHY_CFG_VALUE_CNT];

};



/* PHY AUX config registers */

enum dp_phy_aux_config_type {

	PHY_AUX_CFG0,

	PHY_AUX_CFG1,

	PHY_AUX_CFG2,

	PHY_AUX_CFG3,

	PHY_AUX_CFG4,

	PHY_AUX_CFG5,

	PHY_AUX_CFG6,

	PHY_AUX_CFG7,

	PHY_AUX_CFG8,

	PHY_AUX_CFG9,

	PHY_AUX_CFG_MAX,

};



static inline const char *mdss_dp_get_phy_aux_config_property(u32 cfg_type)

{

	switch (cfg_type) {

	case PHY_AUX_CFG0:

		return "qcom,aux-cfg0-settings";

	case PHY_AUX_CFG1:

		return "qcom,aux-cfg1-settings";

	case PHY_AUX_CFG2:

		return "qcom,aux-cfg2-settings";

	case PHY_AUX_CFG3:

		return "qcom,aux-cfg3-settings";

	case PHY_AUX_CFG4:

		return "qcom,aux-cfg4-settings";

	case PHY_AUX_CFG5:

		return "qcom,aux-cfg5-settings";

	case PHY_AUX_CFG6:

		return "qcom,aux-cfg6-settings";

	case PHY_AUX_CFG7:

		return "qcom,aux-cfg7-settings";

	case PHY_AUX_CFG8:

		return "qcom,aux-cfg8-settings";

	case PHY_AUX_CFG9:

		return "qcom,aux-cfg9-settings";

	default:

		return "unknown";

	}

}



static inline char *mdss_dp_phy_aux_config_type_to_string(u32 cfg_type)

{

	switch (cfg_type) {

	case PHY_AUX_CFG0:

		return DP_ENUM_STR(PHY_AUX_CFG0);

	case PHY_AUX_CFG1:

		return DP_ENUM_STR(PHY_AUX_CFG1);

	case PHY_AUX_CFG2:

		return DP_ENUM_STR(PHY_AUX_CFG2);

	case PHY_AUX_CFG3:

		return DP_ENUM_STR(PHY_AUX_CFG3);

	case PHY_AUX_CFG4:

		return DP_ENUM_STR(PHY_AUX_CFG4);

	case PHY_AUX_CFG5:

		return DP_ENUM_STR(PHY_AUX_CFG5);

	case PHY_AUX_CFG6:

		return DP_ENUM_STR(PHY_AUX_CFG6);

	case PHY_AUX_CFG7:

		return DP_ENUM_STR(PHY_AUX_CFG7);

	case PHY_AUX_CFG8:

		return DP_ENUM_STR(PHY_AUX_CFG8);

	case PHY_AUX_CFG9:

		return DP_ENUM_STR(PHY_AUX_CFG9);

	default:

		return "unknown";

	}

}



struct mdss_dp_drv_pdata {

	/* device driver */

	int (*on) (struct mdss_panel_data *pdata);
@@ -549,7 +628,7 @@ struct mdss_dp_drv_pdata { 


	/* dt settings */

	char l_map[4];

	u32 aux_cfg[AUX_CFG_LEN];

	struct mdss_dp_phy_cfg aux_cfg[PHY_AUX_CFG_MAX];



	struct workqueue_struct *workq;

	struct delayed_work hdcp_cb_work;