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Commit 9aeec63e authored by Ryan Mallon's avatar Ryan Mallon
Browse files

ep93xx: Move EP93XX_SYSCON defines to SoC private header 



The EP93XX_SYSCON defines are now no longer needed outside of the
EP93xx SoC core code, so they can be moved to a private header.

Signed-off-by: default avatarRyan Mallon <rmallon@gmail.com>
Reviewed-by: default avatarMika Westerberg <mika.westerberg@iki.fi>
Acked-by: default avatarHartley Sweeten <hsweeten@visionengravers.com>
parent c444dc07

arch/arm/mach-ep93xx/crunch.c

+2 −0
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@ 
#include <mach/ep93xx-regs.h>

#include <asm/thread_notify.h>



#include "soc.h"



struct crunch_state *crunch_owner;



void crunch_task_release(struct thread_info *thread)

arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h

+0 −89
Original line number Diff line number Diff line
@@ -38,93 +38,4 @@ 
#define EP93XX_UART3_PHYS_BASE		EP93XX_APB_PHYS(0x000e0000)

#define EP93XX_UART3_BASE		EP93XX_APB_IOMEM(0x000e0000)



#define EP93XX_SYSCON_BASE		EP93XX_APB_IOMEM(0x00130000)

#define EP93XX_SYSCON_REG(x)		(EP93XX_SYSCON_BASE + (x))

#define EP93XX_SYSCON_POWER_STATE	EP93XX_SYSCON_REG(0x00)

#define EP93XX_SYSCON_PWRCNT		EP93XX_SYSCON_REG(0x04)

#define EP93XX_SYSCON_PWRCNT_FIR_EN	(1<<31)

#define EP93XX_SYSCON_PWRCNT_UARTBAUD	(1<<29)

#define EP93XX_SYSCON_PWRCNT_USH_EN	(1<<28)

#define EP93XX_SYSCON_PWRCNT_DMA_M2M1	(1<<27)

#define EP93XX_SYSCON_PWRCNT_DMA_M2M0	(1<<26)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P8	(1<<25)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P9	(1<<24)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P6	(1<<23)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P7	(1<<22)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P4	(1<<21)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P5	(1<<20)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P2	(1<<19)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P3	(1<<18)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P0	(1<<17)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P1	(1<<16)

#define EP93XX_SYSCON_HALT		EP93XX_SYSCON_REG(0x08)

#define EP93XX_SYSCON_STANDBY		EP93XX_SYSCON_REG(0x0c)

#define EP93XX_SYSCON_CLKSET1		EP93XX_SYSCON_REG(0x20)

#define EP93XX_SYSCON_CLKSET1_NBYP1	(1<<23)

#define EP93XX_SYSCON_CLKSET2		EP93XX_SYSCON_REG(0x24)

#define EP93XX_SYSCON_CLKSET2_NBYP2	(1<<19)

#define EP93XX_SYSCON_CLKSET2_PLL2_EN	(1<<18)

#define EP93XX_SYSCON_DEVCFG		EP93XX_SYSCON_REG(0x80)

#define EP93XX_SYSCON_DEVCFG_SWRST	(1<<31)

#define EP93XX_SYSCON_DEVCFG_D1ONG	(1<<30)

#define EP93XX_SYSCON_DEVCFG_D0ONG	(1<<29)

#define EP93XX_SYSCON_DEVCFG_IONU2	(1<<28)

#define EP93XX_SYSCON_DEVCFG_GONK	(1<<27)

#define EP93XX_SYSCON_DEVCFG_TONG	(1<<26)

#define EP93XX_SYSCON_DEVCFG_MONG	(1<<25)

#define EP93XX_SYSCON_DEVCFG_U3EN	(1<<24)

#define EP93XX_SYSCON_DEVCFG_CPENA	(1<<23)

#define EP93XX_SYSCON_DEVCFG_A2ONG	(1<<22)

#define EP93XX_SYSCON_DEVCFG_A1ONG	(1<<21)

#define EP93XX_SYSCON_DEVCFG_U2EN	(1<<20)

#define EP93XX_SYSCON_DEVCFG_EXVC	(1<<19)

#define EP93XX_SYSCON_DEVCFG_U1EN	(1<<18)

#define EP93XX_SYSCON_DEVCFG_TIN	(1<<17)

#define EP93XX_SYSCON_DEVCFG_HC3IN	(1<<15)

#define EP93XX_SYSCON_DEVCFG_HC3EN	(1<<14)

#define EP93XX_SYSCON_DEVCFG_HC1IN	(1<<13)

#define EP93XX_SYSCON_DEVCFG_HC1EN	(1<<12)

#define EP93XX_SYSCON_DEVCFG_HONIDE	(1<<11)

#define EP93XX_SYSCON_DEVCFG_GONIDE	(1<<10)

#define EP93XX_SYSCON_DEVCFG_PONG	(1<<9)

#define EP93XX_SYSCON_DEVCFG_EONIDE	(1<<8)

#define EP93XX_SYSCON_DEVCFG_I2SONSSP	(1<<7)

#define EP93XX_SYSCON_DEVCFG_I2SONAC97	(1<<6)

#define EP93XX_SYSCON_DEVCFG_RASONP3	(1<<4)

#define EP93XX_SYSCON_DEVCFG_RAS	(1<<3)

#define EP93XX_SYSCON_DEVCFG_ADCPD	(1<<2)

#define EP93XX_SYSCON_DEVCFG_KEYS	(1<<1)

#define EP93XX_SYSCON_DEVCFG_SHENA	(1<<0)

#define EP93XX_SYSCON_VIDCLKDIV		EP93XX_SYSCON_REG(0x84)

#define EP93XX_SYSCON_CLKDIV_ENABLE	(1<<15)

#define EP93XX_SYSCON_CLKDIV_ESEL	(1<<14)

#define EP93XX_SYSCON_CLKDIV_PSEL	(1<<13)

#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT	8

#define EP93XX_SYSCON_I2SCLKDIV		EP93XX_SYSCON_REG(0x8c)

#define EP93XX_SYSCON_I2SCLKDIV_SENA	(1<<31)

#define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)

#define EP93XX_SYSCON_I2SCLKDIV_SPOL	(1<<19)

#define EP93XX_I2SCLKDIV_SDIV		(1 << 16)

#define EP93XX_I2SCLKDIV_LRDIV32	(0 << 17)

#define EP93XX_I2SCLKDIV_LRDIV64	(1 << 17)

#define EP93XX_I2SCLKDIV_LRDIV128 	(2 << 17)

#define EP93XX_I2SCLKDIV_LRDIV_MASK 	(3 << 17)

#define EP93XX_SYSCON_KEYTCHCLKDIV	EP93XX_SYSCON_REG(0x90)

#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN	(1<<31)

#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV	(1<<16)

#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN	(1<<15)

#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV	(1<<0)

#define EP93XX_SYSCON_SYSCFG		EP93XX_SYSCON_REG(0x9c)

#define EP93XX_SYSCON_SYSCFG_REV_MASK	(0xf0000000)

#define EP93XX_SYSCON_SYSCFG_REV_SHIFT	(28)

#define EP93XX_SYSCON_SYSCFG_SBOOT	(1<<8)

#define EP93XX_SYSCON_SYSCFG_LCSN7	(1<<7)

#define EP93XX_SYSCON_SYSCFG_LCSN6	(1<<6)

#define EP93XX_SYSCON_SYSCFG_LASDO	(1<<5)

#define EP93XX_SYSCON_SYSCFG_LEEDA	(1<<4)

#define EP93XX_SYSCON_SYSCFG_LEECLK	(1<<3)

#define EP93XX_SYSCON_SYSCFG_LCSN2	(1<<1)

#define EP93XX_SYSCON_SYSCFG_LCSN1	(1<<0)

#define EP93XX_SYSCON_SWLOCK		EP93XX_SYSCON_REG(0xc0)



#endif

arch/arm/mach-ep93xx/soc.h

+90 −0
Original line number Diff line number Diff line
@@ -104,6 +104,96 @@ 
#define EP93XX_WATCHDOG_PHYS_BASE	EP93XX_APB_PHYS(0x00140000)

#define EP93XX_WATCHDOG_BASE		EP93XX_APB_IOMEM(0x00140000)



/* System controller */

#define EP93XX_SYSCON_BASE		EP93XX_APB_IOMEM(0x00130000)

#define EP93XX_SYSCON_REG(x)		(EP93XX_SYSCON_BASE + (x))

#define EP93XX_SYSCON_POWER_STATE	EP93XX_SYSCON_REG(0x00)

#define EP93XX_SYSCON_PWRCNT		EP93XX_SYSCON_REG(0x04)

#define EP93XX_SYSCON_PWRCNT_FIR_EN	(1<<31)

#define EP93XX_SYSCON_PWRCNT_UARTBAUD	(1<<29)

#define EP93XX_SYSCON_PWRCNT_USH_EN	(1<<28)

#define EP93XX_SYSCON_PWRCNT_DMA_M2M1	(1<<27)

#define EP93XX_SYSCON_PWRCNT_DMA_M2M0	(1<<26)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P8	(1<<25)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P9	(1<<24)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P6	(1<<23)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P7	(1<<22)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P4	(1<<21)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P5	(1<<20)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P2	(1<<19)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P3	(1<<18)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P0	(1<<17)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P1	(1<<16)

#define EP93XX_SYSCON_HALT		EP93XX_SYSCON_REG(0x08)

#define EP93XX_SYSCON_STANDBY		EP93XX_SYSCON_REG(0x0c)

#define EP93XX_SYSCON_CLKSET1		EP93XX_SYSCON_REG(0x20)

#define EP93XX_SYSCON_CLKSET1_NBYP1	(1<<23)

#define EP93XX_SYSCON_CLKSET2		EP93XX_SYSCON_REG(0x24)

#define EP93XX_SYSCON_CLKSET2_NBYP2	(1<<19)

#define EP93XX_SYSCON_CLKSET2_PLL2_EN	(1<<18)

#define EP93XX_SYSCON_DEVCFG		EP93XX_SYSCON_REG(0x80)

#define EP93XX_SYSCON_DEVCFG_SWRST	(1<<31)

#define EP93XX_SYSCON_DEVCFG_D1ONG	(1<<30)

#define EP93XX_SYSCON_DEVCFG_D0ONG	(1<<29)

#define EP93XX_SYSCON_DEVCFG_IONU2	(1<<28)

#define EP93XX_SYSCON_DEVCFG_GONK	(1<<27)

#define EP93XX_SYSCON_DEVCFG_TONG	(1<<26)

#define EP93XX_SYSCON_DEVCFG_MONG	(1<<25)

#define EP93XX_SYSCON_DEVCFG_U3EN	(1<<24)

#define EP93XX_SYSCON_DEVCFG_CPENA	(1<<23)

#define EP93XX_SYSCON_DEVCFG_A2ONG	(1<<22)

#define EP93XX_SYSCON_DEVCFG_A1ONG	(1<<21)

#define EP93XX_SYSCON_DEVCFG_U2EN	(1<<20)

#define EP93XX_SYSCON_DEVCFG_EXVC	(1<<19)

#define EP93XX_SYSCON_DEVCFG_U1EN	(1<<18)

#define EP93XX_SYSCON_DEVCFG_TIN	(1<<17)

#define EP93XX_SYSCON_DEVCFG_HC3IN	(1<<15)

#define EP93XX_SYSCON_DEVCFG_HC3EN	(1<<14)

#define EP93XX_SYSCON_DEVCFG_HC1IN	(1<<13)

#define EP93XX_SYSCON_DEVCFG_HC1EN	(1<<12)

#define EP93XX_SYSCON_DEVCFG_HONIDE	(1<<11)

#define EP93XX_SYSCON_DEVCFG_GONIDE	(1<<10)

#define EP93XX_SYSCON_DEVCFG_PONG	(1<<9)

#define EP93XX_SYSCON_DEVCFG_EONIDE	(1<<8)

#define EP93XX_SYSCON_DEVCFG_I2SONSSP	(1<<7)

#define EP93XX_SYSCON_DEVCFG_I2SONAC97	(1<<6)

#define EP93XX_SYSCON_DEVCFG_RASONP3	(1<<4)

#define EP93XX_SYSCON_DEVCFG_RAS	(1<<3)

#define EP93XX_SYSCON_DEVCFG_ADCPD	(1<<2)

#define EP93XX_SYSCON_DEVCFG_KEYS	(1<<1)

#define EP93XX_SYSCON_DEVCFG_SHENA	(1<<0)

#define EP93XX_SYSCON_VIDCLKDIV		EP93XX_SYSCON_REG(0x84)

#define EP93XX_SYSCON_CLKDIV_ENABLE	(1<<15)

#define EP93XX_SYSCON_CLKDIV_ESEL	(1<<14)

#define EP93XX_SYSCON_CLKDIV_PSEL	(1<<13)

#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT	8

#define EP93XX_SYSCON_I2SCLKDIV		EP93XX_SYSCON_REG(0x8c)

#define EP93XX_SYSCON_I2SCLKDIV_SENA	(1<<31)

#define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)

#define EP93XX_SYSCON_I2SCLKDIV_SPOL	(1<<19)

#define EP93XX_I2SCLKDIV_SDIV		(1 << 16)

#define EP93XX_I2SCLKDIV_LRDIV32	(0 << 17)

#define EP93XX_I2SCLKDIV_LRDIV64	(1 << 17)

#define EP93XX_I2SCLKDIV_LRDIV128	(2 << 17)

#define EP93XX_I2SCLKDIV_LRDIV_MASK	(3 << 17)

#define EP93XX_SYSCON_KEYTCHCLKDIV	EP93XX_SYSCON_REG(0x90)

#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN	(1<<31)

#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV	(1<<16)

#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN	(1<<15)

#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV	(1<<0)

#define EP93XX_SYSCON_SYSCFG		EP93XX_SYSCON_REG(0x9c)

#define EP93XX_SYSCON_SYSCFG_REV_MASK	(0xf0000000)

#define EP93XX_SYSCON_SYSCFG_REV_SHIFT	(28)

#define EP93XX_SYSCON_SYSCFG_SBOOT	(1<<8)

#define EP93XX_SYSCON_SYSCFG_LCSN7	(1<<7)

#define EP93XX_SYSCON_SYSCFG_LCSN6	(1<<6)

#define EP93XX_SYSCON_SYSCFG_LASDO	(1<<5)

#define EP93XX_SYSCON_SYSCFG_LEEDA	(1<<4)

#define EP93XX_SYSCON_SYSCFG_LEECLK	(1<<3)

#define EP93XX_SYSCON_SYSCFG_LCSN2	(1<<1)

#define EP93XX_SYSCON_SYSCFG_LCSN1	(1<<0)

#define EP93XX_SYSCON_SWLOCK		EP93XX_SYSCON_REG(0xc0)



/* EP93xx System Controller software locked register write */

void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);

void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);