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Commit 99682cfc authored by Rashi Bindra's avatar Rashi Bindra
Browse files

clk: qcom: Remove the CLK_SET_RATE_PARENT flag for Byte intferface clk 



If the CLK_SET_RATE_PARENT flag for the mmss_mdss_byte_intf_div_clk
divider is set re-calculation of dividers in DSI byte clock path takes
place which causes both the byte clock and byte interface clock to be
set to the same value.

Change-Id: Ia30c8070ec5c451a12f29e983089a7a2bbe6a8b3
Signed-off-by: default avatarRashi Bindra <rbindra@codeaurora.org>
parent 2c333d31

drivers/clk/qcom/mmcc-sdm660.c

+3 −3
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -2419,7 +2419,7 @@ static struct clk_regmap_div mmss_mdss_byte0_intf_div_clk = { 
			},

			.num_parents = 1,

			.ops = &clk_regmap_div_ops,

			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

			.flags = CLK_GET_RATE_NOCACHE,

		},

	},

};
@@ -2476,7 +2476,7 @@ static struct clk_regmap_div mmss_mdss_byte1_intf_div_clk = { 
			},

			.num_parents = 1,

			.ops = &clk_regmap_div_ops,

			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

			.flags = CLK_GET_RATE_NOCACHE,

		},

	},

};