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Commit 96b30ff1 authored by Srinivas Ramana's avatar Srinivas Ramana
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Documentation: edac: Add bindings for arm64 cpu erp 



This is a snapshot from msm-3.18 upto the
commit 262b8c5814ec ("edac: cortex_arm64_edac:
modify sbe detection to use perf events") for the
arm64 cache cpu erp bindings.

Change-Id: I7313a121440bf5a455401cf73bd5ef4d6c1506cb
Signed-off-by: default avatarSrinivas Ramana <sramana@codeaurora.org>
parent 8a4f90bd

Documentation/devicetree/bindings/cache/arm64_cache_erp.txt

0 → 100644
+34 −0
Original line number Diff line number Diff line 
* ARM Cortex A53 / A57 cache error reporting driver



Required properties:

- compatible: Should be "arm,arm64-cpu-erp"

- interrupts: List of hardware interrupts that may indicate an error condition

  in the CPU subsystem, or in the L1 / L2 caches. At least one interrupt entry

  is required.

- interrupt-names: Must contain one or more of the following IRQ types:

	"pri-dbe-irq" - double-bit error interrupt for primary cluster

	"sec-dbe-irq" - double-bit error interrupt for secondary cluster

	"pri-ext-irq" - external bus error interrupt for primary cluster

	"sec-ext-irq" - external bus error interrupt for secondary cluster

	"cci-irq"     - CCI error interrupt. If this property is present, having

			the 'cci' reg-base defined using the 'reg' property is

			recommended.

	At least one irq entry is required.



Optional properties:

- reg: Should contain physical address of the CCI register space

- reg-names: Should contain 'cci'. Must be present if 'reg' property is present

- poll-delay-msec: Indicates how often the edac check callback should be called. Time in msec.



Example:

	cpu_cache_erp {

		compatible = "arm,arm64-cpu-erp";

		interrupt-names = "pri-dbe-irq",

				  "sec-dbe-irq",

				  "pri-ext-irq",

				  "sec-ext-irq";

		interrupts = <0 92 0>,

			     <0 91 0>,

			     <0 96 0>,

			     <0 95 0>;

	};