edac: Convert debugfX to edac_dbg(X, (956b9ba1) · Commits · e / devices / android_kernel_sony_msm8998

drivers/edac/amd64_edac.c

+132 −138

Original line number	Original line	Diff line number	Diff line
	@@ -321,7 +321,7 @@ found:
	return edac_mc_find((int)node_id);		return edac_mc_find((int)node_id);

	err_no_match:		err_no_match:
	debugf2("sys_addr 0x%lx doesn't match any node\n",		edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",
	(unsigned long)sys_addr);		(unsigned long)sys_addr);

	return NULL;		return NULL;
	@@ -393,14 +393,14 @@ static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
	mask = ~mask;		mask = ~mask;

	if ((input_addr & mask) == (base & mask)) {		if ((input_addr & mask) == (base & mask)) {
	debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n",		edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n",
	(unsigned long)input_addr, csrow,		(unsigned long)input_addr, csrow,
	pvt->mc_node_id);		pvt->mc_node_id);

	return csrow;		return csrow;
	}		}
	}		}
	debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n",		edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n",
	(unsigned long)input_addr, pvt->mc_node_id);		(unsigned long)input_addr, pvt->mc_node_id);

	return -1;		return -1;
	@@ -430,19 +430,19 @@ int amd64_get_dram_hole_info(struct mem_ctl_info mci, u64 hole_base,

	/* only revE and later have the DRAM Hole Address Register */		/* only revE and later have the DRAM Hole Address Register */
	if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_E) {		if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_E) {
	debugf1(" revision %d for node %d does not support DHAR\n",		edac_dbg(1, " revision %d for node %d does not support DHAR\n",
	pvt->ext_model, pvt->mc_node_id);		pvt->ext_model, pvt->mc_node_id);
	return 1;		return 1;
	}		}

	/* valid for Fam10h and above */		/* valid for Fam10h and above */
	if (boot_cpu_data.x86 >= 0x10 && !dhar_mem_hoist_valid(pvt)) {		if (boot_cpu_data.x86 >= 0x10 && !dhar_mem_hoist_valid(pvt)) {
	debugf1(" Dram Memory Hoisting is DISABLED on this system\n");		edac_dbg(1, " Dram Memory Hoisting is DISABLED on this system\n");
	return 1;		return 1;
	}		}

	if (!dhar_valid(pvt)) {		if (!dhar_valid(pvt)) {
	debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n",		edac_dbg(1, " Dram Memory Hoisting is DISABLED on this node %d\n",
	pvt->mc_node_id);		pvt->mc_node_id);
	return 1;		return 1;
	}		}
	@@ -475,7 +475,7 @@ int amd64_get_dram_hole_info(struct mem_ctl_info mci, u64 hole_base,
	else		else
	*hole_offset = k8_dhar_offset(pvt);		*hole_offset = k8_dhar_offset(pvt);

	debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",		edac_dbg(1, " DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
	pvt->mc_node_id, (unsigned long)*hole_base,		pvt->mc_node_id, (unsigned long)*hole_base,
	(unsigned long)hole_offset, (unsigned long)hole_size);		(unsigned long)hole_offset, (unsigned long)hole_size);

	@@ -528,8 +528,7 @@ static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
	/* use DHAR to translate SysAddr to DramAddr */		/* use DHAR to translate SysAddr to DramAddr */
	dram_addr = sys_addr - hole_offset;		dram_addr = sys_addr - hole_offset;

	debugf2("using DHAR to translate SysAddr 0x%lx to "		edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
	"DramAddr 0x%lx\n",
	(unsigned long)sys_addr,		(unsigned long)sys_addr,
	(unsigned long)dram_addr);		(unsigned long)dram_addr);

	@@ -548,9 +547,8 @@ static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
	*/		*/
	dram_addr = (sys_addr & GENMASK(0, 39)) - dram_base;		dram_addr = (sys_addr & GENMASK(0, 39)) - dram_base;

	debugf2("using DRAM Base register to translate SysAddr 0x%lx to "		edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
	"DramAddr 0x%lx\n", (unsigned long)sys_addr,		(unsigned long)sys_addr, (unsigned long)dram_addr);
	(unsigned long)dram_addr);
	return dram_addr;		return dram_addr;
	}		}

	@@ -586,7 +584,7 @@ static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr)
	input_addr = ((dram_addr >> intlv_shift) & GENMASK(12, 35)) +		input_addr = ((dram_addr >> intlv_shift) & GENMASK(12, 35)) +
	(dram_addr & 0xfff);		(dram_addr & 0xfff);

	debugf2(" Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",		edac_dbg(2, " Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
	intlv_shift, (unsigned long)dram_addr,		intlv_shift, (unsigned long)dram_addr,
	(unsigned long)input_addr);		(unsigned long)input_addr);

	@@ -604,7 +602,7 @@ static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
	input_addr =		input_addr =
	dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr));		dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr));

	debugf2("SysAdddr 0x%lx translates to InputAddr 0x%lx\n",		edac_dbg(2, "SysAdddr 0x%lx translates to InputAddr 0x%lx\n",
	(unsigned long)sys_addr, (unsigned long)input_addr);		(unsigned long)sys_addr, (unsigned long)input_addr);

	return input_addr;		return input_addr;
	@@ -637,8 +635,8 @@ static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)

	intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));		intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
	if (intlv_shift == 0) {		if (intlv_shift == 0) {
	debugf1(" InputAddr 0x%lx translates to DramAddr of "		edac_dbg(1, " InputAddr 0x%lx translates to DramAddr of same value\n",
	"same value\n", (unsigned long)input_addr);		(unsigned long)input_addr);

	return input_addr;		return input_addr;
	}		}
	@@ -649,8 +647,8 @@ static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)
	intlv_sel = dram_intlv_sel(pvt, node_id) & ((1 << intlv_shift) - 1);		intlv_sel = dram_intlv_sel(pvt, node_id) & ((1 << intlv_shift) - 1);
	dram_addr = bits + (intlv_sel << 12);		dram_addr = bits + (intlv_sel << 12);

	debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx "		edac_dbg(1, "InputAddr 0x%lx translates to DramAddr 0x%lx (%d node interleave bits)\n",
	"(%d node interleave bits)\n", (unsigned long)input_addr,		(unsigned long)input_addr,
	(unsigned long)dram_addr, intlv_shift);		(unsigned long)dram_addr, intlv_shift);

	return dram_addr;		return dram_addr;
	@@ -673,8 +671,8 @@ static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr)
	(dram_addr < (hole_base + hole_size))) {		(dram_addr < (hole_base + hole_size))) {
	sys_addr = dram_addr + hole_offset;		sys_addr = dram_addr + hole_offset;

	debugf1("using DHAR to translate DramAddr 0x%lx to "		edac_dbg(1, "using DHAR to translate DramAddr 0x%lx to SysAddr 0x%lx\n",
	"SysAddr 0x%lx\n", (unsigned long)dram_addr,		(unsigned long)dram_addr,
	(unsigned long)sys_addr);		(unsigned long)sys_addr);

	return sys_addr;		return sys_addr;
	@@ -697,7 +695,7 @@ static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr)
	*/		*/
	sys_addr \|= ~((sys_addr & (1ull << 39)) - 1);		sys_addr \|= ~((sys_addr & (1ull << 39)) - 1);

	debugf1(" Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n",		edac_dbg(1, " Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n",
	pvt->mc_node_id, (unsigned long)dram_addr,		pvt->mc_node_id, (unsigned long)dram_addr,
	(unsigned long)sys_addr);		(unsigned long)sys_addr);

	@@ -768,20 +766,20 @@ static void amd64_debug_display_dimm_sizes(struct amd64_pvt *, u8);

	static void amd64_dump_dramcfg_low(u32 dclr, int chan)		static void amd64_dump_dramcfg_low(u32 dclr, int chan)
	{		{
	debugf1("F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);		edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);

	debugf1(" DIMM type: %sbuffered; all DIMMs support ECC: %s\n",		edac_dbg(1, " DIMM type: %sbuffered; all DIMMs support ECC: %s\n",
	(dclr & BIT(16)) ? "un" : "",		(dclr & BIT(16)) ? "un" : "",
	(dclr & BIT(19)) ? "yes" : "no");		(dclr & BIT(19)) ? "yes" : "no");

	debugf1(" PAR/ERR parity: %s\n",		edac_dbg(1, " PAR/ERR parity: %s\n",
	(dclr & BIT(8)) ? "enabled" : "disabled");		(dclr & BIT(8)) ? "enabled" : "disabled");

	if (boot_cpu_data.x86 == 0x10)		if (boot_cpu_data.x86 == 0x10)
	debugf1(" DCT 128bit mode width: %s\n",		edac_dbg(1, " DCT 128bit mode width: %s\n",
	(dclr & BIT(11)) ? "128b" : "64b");		(dclr & BIT(11)) ? "128b" : "64b");

	debugf1(" x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",		edac_dbg(1, " x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
	(dclr & BIT(12)) ? "yes" : "no",		(dclr & BIT(12)) ? "yes" : "no",
	(dclr & BIT(13)) ? "yes" : "no",		(dclr & BIT(13)) ? "yes" : "no",
	(dclr & BIT(14)) ? "yes" : "no",		(dclr & BIT(14)) ? "yes" : "no",
	@@ -791,26 +789,25 @@ static void amd64_dump_dramcfg_low(u32 dclr, int chan)
	/* Display and decode various NB registers for debug purposes. */		/* Display and decode various NB registers for debug purposes. */
	static void dump_misc_regs(struct amd64_pvt *pvt)		static void dump_misc_regs(struct amd64_pvt *pvt)
	{		{
	debugf1("F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);		edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);

	debugf1(" NB two channel DRAM capable: %s\n",		edac_dbg(1, " NB two channel DRAM capable: %s\n",
	(pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");		(pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");

	debugf1(" ECC capable: %s, ChipKill ECC capable: %s\n",		edac_dbg(1, " ECC capable: %s, ChipKill ECC capable: %s\n",
	(pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",		(pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
	(pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");		(pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");

	amd64_dump_dramcfg_low(pvt->dclr0, 0);		amd64_dump_dramcfg_low(pvt->dclr0, 0);

	debugf1("F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);		edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);

	debugf1("F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, "		edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n",
	"offset: 0x%08x\n",
	pvt->dhar, dhar_base(pvt),		pvt->dhar, dhar_base(pvt),
	(boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt)		(boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt)
	: f10_dhar_offset(pvt));		: f10_dhar_offset(pvt));

	debugf1(" DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");		edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");

	amd64_debug_display_dimm_sizes(pvt, 0);		amd64_debug_display_dimm_sizes(pvt, 0);

	@@ -857,14 +854,14 @@ static void read_dct_base_mask(struct amd64_pvt *pvt)
	u32 *base1 = &pvt->csels[1].csbases[cs];		u32 *base1 = &pvt->csels[1].csbases[cs];

	if (!amd64_read_dct_pci_cfg(pvt, reg0, base0))		if (!amd64_read_dct_pci_cfg(pvt, reg0, base0))
	debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n",		edac_dbg(0, " DCSB0[%d]=0x%08x reg: F2x%x\n",
	cs, *base0, reg0);		cs, *base0, reg0);

	if (boot_cpu_data.x86 == 0xf \|\| dct_ganging_enabled(pvt))		if (boot_cpu_data.x86 == 0xf \|\| dct_ganging_enabled(pvt))
	continue;		continue;

	if (!amd64_read_dct_pci_cfg(pvt, reg1, base1))		if (!amd64_read_dct_pci_cfg(pvt, reg1, base1))
	debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n",		edac_dbg(0, " DCSB1[%d]=0x%08x reg: F2x%x\n",
	cs, *base1, reg1);		cs, *base1, reg1);
	}		}

	@@ -875,14 +872,14 @@ static void read_dct_base_mask(struct amd64_pvt *pvt)
	u32 *mask1 = &pvt->csels[1].csmasks[cs];		u32 *mask1 = &pvt->csels[1].csmasks[cs];

	if (!amd64_read_dct_pci_cfg(pvt, reg0, mask0))		if (!amd64_read_dct_pci_cfg(pvt, reg0, mask0))
	debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n",		edac_dbg(0, " DCSM0[%d]=0x%08x reg: F2x%x\n",
	cs, *mask0, reg0);		cs, *mask0, reg0);

	if (boot_cpu_data.x86 == 0xf \|\| dct_ganging_enabled(pvt))		if (boot_cpu_data.x86 == 0xf \|\| dct_ganging_enabled(pvt))
	continue;		continue;

	if (!amd64_read_dct_pci_cfg(pvt, reg1, mask1))		if (!amd64_read_dct_pci_cfg(pvt, reg1, mask1))
	debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n",		edac_dbg(0, " DCSM1[%d]=0x%08x reg: F2x%x\n",
	cs, *mask1, reg1);		cs, *mask1, reg1);
	}		}
	}		}
	@@ -1193,7 +1190,7 @@ static int f1x_early_channel_count(struct amd64_pvt *pvt)
	* Need to check DCT0[0] and DCT1[0] to see if only one of them has		* Need to check DCT0[0] and DCT1[0] to see if only one of them has
	* their CSEnable bit on. If so, then SINGLE DIMM case.		* their CSEnable bit on. If so, then SINGLE DIMM case.
	*/		*/
	debugf0("Data width is not 128 bits - need more decoding\n");		edac_dbg(0, "Data width is not 128 bits - need more decoding\n");

	/*		/*
	* Check DRAM Bank Address Mapping values for each DIMM to see if there		* Check DRAM Bank Address Mapping values for each DIMM to see if there
	@@ -1272,22 +1269,21 @@ static void read_dram_ctl_register(struct amd64_pvt *pvt)
	return;		return;

	if (!amd64_read_dct_pci_cfg(pvt, DCT_SEL_LO, &pvt->dct_sel_lo)) {		if (!amd64_read_dct_pci_cfg(pvt, DCT_SEL_LO, &pvt->dct_sel_lo)) {
	debugf0("F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",		edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
	pvt->dct_sel_lo, dct_sel_baseaddr(pvt));		pvt->dct_sel_lo, dct_sel_baseaddr(pvt));

	debugf0(" DCTs operate in %s mode.\n",		edac_dbg(0, " DCTs operate in %s mode\n",
	(dct_ganging_enabled(pvt) ? "ganged" : "unganged"));		(dct_ganging_enabled(pvt) ? "ganged" : "unganged"));

	if (!dct_ganging_enabled(pvt))		if (!dct_ganging_enabled(pvt))
	debugf0(" Address range split per DCT: %s\n",		edac_dbg(0, " Address range split per DCT: %s\n",
	(dct_high_range_enabled(pvt) ? "yes" : "no"));		(dct_high_range_enabled(pvt) ? "yes" : "no"));

	debugf0(" data interleave for ECC: %s, "		edac_dbg(0, " data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",
	"DRAM cleared since last warm reset: %s\n",
	(dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),		(dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
	(dct_memory_cleared(pvt) ? "yes" : "no"));		(dct_memory_cleared(pvt) ? "yes" : "no"));

	debugf0(" channel interleave: %s, "		edac_dbg(0, " channel interleave: %s, "
	"interleave bits selector: 0x%x\n",		"interleave bits selector: 0x%x\n",
	(dct_interleave_enabled(pvt) ? "enabled" : "disabled"),		(dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
	dct_sel_interleave_addr(pvt));		dct_sel_interleave_addr(pvt));
	@@ -1428,7 +1424,7 @@ static int f1x_lookup_addr_in_dct(u64 in_addr, u32 nid, u8 dct)

	pvt = mci->pvt_info;		pvt = mci->pvt_info;

	debugf1("input addr: 0x%llx, DCT: %d\n", in_addr, dct);		edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct);

	for_each_chip_select(csrow, dct, pvt) {		for_each_chip_select(csrow, dct, pvt) {
	if (!csrow_enabled(csrow, dct, pvt))		if (!csrow_enabled(csrow, dct, pvt))
	@@ -1436,19 +1432,18 @@ static int f1x_lookup_addr_in_dct(u64 in_addr, u32 nid, u8 dct)

	get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask);		get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask);

	debugf1(" CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",		edac_dbg(1, " CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",
	csrow, cs_base, cs_mask);		csrow, cs_base, cs_mask);

	cs_mask = ~cs_mask;		cs_mask = ~cs_mask;

	debugf1(" (InputAddr & ~CSMask)=0x%llx "		edac_dbg(1, " (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n",
	"(CSBase & ~CSMask)=0x%llx\n",
	(in_addr & cs_mask), (cs_base & cs_mask));		(in_addr & cs_mask), (cs_base & cs_mask));

	if ((in_addr & cs_mask) == (cs_base & cs_mask)) {		if ((in_addr & cs_mask) == (cs_base & cs_mask)) {
	cs_found = f10_process_possible_spare(pvt, dct, csrow);		cs_found = f10_process_possible_spare(pvt, dct, csrow);

	debugf1(" MATCH csrow=%d\n", cs_found);		edac_dbg(1, " MATCH csrow=%d\n", cs_found);
	break;		break;
	}		}
	}		}
	@@ -1505,7 +1500,7 @@ static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
	u8 intlv_en = dram_intlv_en(pvt, range);		u8 intlv_en = dram_intlv_en(pvt, range);
	u32 intlv_sel = dram_intlv_sel(pvt, range);		u32 intlv_sel = dram_intlv_sel(pvt, range);

	debugf1("(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",		edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
	range, sys_addr, get_dram_limit(pvt, range));		range, sys_addr, get_dram_limit(pvt, range));

	if (dhar_valid(pvt) &&		if (dhar_valid(pvt) &&
	@@ -1562,7 +1557,7 @@ static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
	(chan_addr & 0xfff);		(chan_addr & 0xfff);
	}		}

	debugf1(" Normalized DCT addr: 0x%llx\n", chan_addr);		edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr);

	cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel);		cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel);

	@@ -1664,7 +1659,8 @@ static void amd64_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
	dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->csels[1].csbases		dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->csels[1].csbases
	: pvt->csels[0].csbases;		: pvt->csels[0].csbases;

	debugf1("F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n", ctrl, dbam);		edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
			ctrl, dbam);

	edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);		edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);

	@@ -1840,7 +1836,7 @@ static int decode_syndrome(u16 syndrome, u16 *vectors, unsigned num_vecs,
	}		}
	}		}

	debugf0("syndrome(%x) not found\n", syndrome);		edac_dbg(0, "syndrome(%x) not found\n", syndrome);
	return -1;		return -1;
	}		}

	@@ -2047,9 +2043,9 @@ static int reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 f1_id, u16 f3_id)

	return -ENODEV;		return -ENODEV;
	}		}
	debugf1("F1: %s\n", pci_name(pvt->F1));		edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));
	debugf1("F2: %s\n", pci_name(pvt->F2));		edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));
	debugf1("F3: %s\n", pci_name(pvt->F3));		edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));

	return 0;		return 0;
	}		}
	@@ -2076,15 +2072,15 @@ static void read_mc_regs(struct amd64_pvt *pvt)
	* those are Read-As-Zero		* those are Read-As-Zero
	*/		*/
	rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem);		rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem);
	debugf0(" TOP_MEM: 0x%016llx\n", pvt->top_mem);		edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem);

	/* check first whether TOP_MEM2 is enabled */		/* check first whether TOP_MEM2 is enabled */
	rdmsrl(MSR_K8_SYSCFG, msr_val);		rdmsrl(MSR_K8_SYSCFG, msr_val);
	if (msr_val & (1U << 21)) {		if (msr_val & (1U << 21)) {
	rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2);		rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2);
	debugf0(" TOP_MEM2: 0x%016llx\n", pvt->top_mem2);		edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
	} else		} else
	debugf0(" TOP_MEM2 disabled.\n");		edac_dbg(0, " TOP_MEM2 disabled\n");

	amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);		amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);

	@@ -2100,12 +2096,12 @@ static void read_mc_regs(struct amd64_pvt *pvt)
	if (!rw)		if (!rw)
	continue;		continue;

	debugf1(" DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",		edac_dbg(1, " DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",
	range,		range,
	get_dram_base(pvt, range),		get_dram_base(pvt, range),
	get_dram_limit(pvt, range));		get_dram_limit(pvt, range));

	debugf1(" IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",		edac_dbg(1, " IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",
	dram_intlv_en(pvt, range) ? "Enabled" : "Disabled",		dram_intlv_en(pvt, range) ? "Enabled" : "Disabled",
	(rw & 0x1) ? "R" : "-",		(rw & 0x1) ? "R" : "-",
	(rw & 0x2) ? "W" : "-",		(rw & 0x2) ? "W" : "-",
	@@ -2191,8 +2187,8 @@ static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)

	nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT);		nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT);

	debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode);		edac_dbg(0, " (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode);
	debugf0(" nr_pages/channel= %u channel-count = %d\n",		edac_dbg(0, " nr_pages/channel= %u channel-count = %d\n",
	nr_pages, pvt->channel_count);		nr_pages, pvt->channel_count);

	return nr_pages;		return nr_pages;
	@@ -2218,7 +2214,7 @@ static int init_csrows(struct mem_ctl_info *mci)

	pvt->nbcfg = val;		pvt->nbcfg = val;

	debugf0("node %d, NBCFG=0x%08x[ChipKillEccCap: %d\|DramEccEn: %d]\n",		edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d\|DramEccEn: %d]\n",
	pvt->mc_node_id, val,		pvt->mc_node_id, val,
	!!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));		!!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));

	@@ -2226,14 +2222,11 @@ static int init_csrows(struct mem_ctl_info *mci)
	csrow = mci->csrows[i];		csrow = mci->csrows[i];

	if (!csrow_enabled(i, 0, pvt) && !csrow_enabled(i, 1, pvt)) {		if (!csrow_enabled(i, 0, pvt) && !csrow_enabled(i, 1, pvt)) {
	debugf1("----CSROW %d EMPTY for node %d\n", i,		edac_dbg(1, "----CSROW %d VALID for MC node %d\n",
	pvt->mc_node_id);		i, pvt->mc_node_id);
	continue;		continue;
	}		}

	debugf1("----CSROW %d VALID for MC node %d\n",
	i, pvt->mc_node_id);

	empty = 0;		empty = 0;
	if (csrow_enabled(i, 0, pvt))		if (csrow_enabled(i, 0, pvt))
	nr_pages = amd64_csrow_nr_pages(pvt, 0, i);		nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
	@@ -2245,8 +2238,9 @@ static int init_csrows(struct mem_ctl_info *mci)

	mtype = amd64_determine_memory_type(pvt, i);		mtype = amd64_determine_memory_type(pvt, i);

	debugf1(" for MC node %d csrow %d:\n", pvt->mc_node_id, i);		edac_dbg(1, " for MC node %d csrow %d:\n", pvt->mc_node_id, i);
	debugf1(" nr_pages: %u\n", nr_pages * pvt->channel_count);		edac_dbg(1, " nr_pages: %u\n",
			nr_pages * pvt->channel_count);

	/*		/*
	* determine whether CHIPKILL or JUST ECC or NO ECC is operating		* determine whether CHIPKILL or JUST ECC or NO ECC is operating
	@@ -2298,7 +2292,7 @@ static bool amd64_nb_mce_bank_enabled_on_node(unsigned nid)
	struct msr *reg = per_cpu_ptr(msrs, cpu);		struct msr *reg = per_cpu_ptr(msrs, cpu);
	nbe = reg->l & MSR_MCGCTL_NBE;		nbe = reg->l & MSR_MCGCTL_NBE;

	debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",		edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
	cpu, reg->q,		cpu, reg->q,
	(nbe ? "enabled" : "disabled"));		(nbe ? "enabled" : "disabled"));

	@@ -2371,7 +2365,7 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,

	amd64_read_pci_cfg(F3, NBCFG, &value);		amd64_read_pci_cfg(F3, NBCFG, &value);

	debugf0("1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",		edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
	nid, value, !!(value & NBCFG_ECC_ENABLE));		nid, value, !!(value & NBCFG_ECC_ENABLE));

	if (!(value & NBCFG_ECC_ENABLE)) {		if (!(value & NBCFG_ECC_ENABLE)) {
	@@ -2396,7 +2390,7 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,
	s->flags.nb_ecc_prev = 1;		s->flags.nb_ecc_prev = 1;
	}		}

	debugf0("2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",		edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
	nid, value, !!(value & NBCFG_ECC_ENABLE));		nid, value, !!(value & NBCFG_ECC_ENABLE));

	return ret;		return ret;
	@@ -2615,11 +2609,11 @@ static int amd64_init_one_instance(struct pci_dev *F2)

	ret = -ENODEV;		ret = -ENODEV;
	if (edac_mc_add_mc(mci)) {		if (edac_mc_add_mc(mci)) {
	debugf1("failed edac_mc_add_mc()\n");		edac_dbg(1, "failed edac_mc_add_mc()\n");
	goto err_add_mc;		goto err_add_mc;
	}		}
	if (set_mc_sysfs_attrs(mci)) {		if (set_mc_sysfs_attrs(mci)) {
	debugf1("failed edac_mc_add_mc()\n");		edac_dbg(1, "failed edac_mc_add_mc()\n");
	goto err_add_sysfs;		goto err_add_sysfs;
	}		}

	@@ -2660,7 +2654,7 @@ static int __devinit amd64_probe_one_instance(struct pci_dev *pdev,

	ret = pci_enable_device(pdev);		ret = pci_enable_device(pdev);
	if (ret < 0) {		if (ret < 0) {
	debugf0("ret=%d\n", ret);		edac_dbg(0, "ret=%d\n", ret);
	return -EIO;		return -EIO;
	}		}

drivers/edac/amd64_edac_inj.c

+4 −2

Original line number	Original line	Diff line number	Diff line
	@@ -142,7 +142,8 @@ static ssize_t amd64_inject_read_store(struct device *dev,
	/* Issue 'word' and 'bit' along with the READ request */		/* Issue 'word' and 'bit' along with the READ request */
	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);		amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);

	debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);		edac_dbg(0, "section=0x%x word_bits=0x%x\n",
			section, word_bits);

	return count;		return count;
	}		}
	@@ -177,7 +178,8 @@ static ssize_t amd64_inject_write_store(struct device *dev,
	/* Issue 'word' and 'bit' along with the READ request */		/* Issue 'word' and 'bit' along with the READ request */
	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);		amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);

	debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);		edac_dbg(0, "section=0x%x word_bits=0x%x\n",
			section, word_bits);

	return count;		return count;
	}		}

drivers/edac/amd76x_edac.c

+7 −7

Original line number	Original line	Diff line number	Diff line
	@@ -180,7 +180,7 @@ static int amd76x_process_error_info(struct mem_ctl_info *mci,
	static void amd76x_check(struct mem_ctl_info *mci)		static void amd76x_check(struct mem_ctl_info *mci)
	{		{
	struct amd76x_error_info info;		struct amd76x_error_info info;
	debugf3("\n");		edac_dbg(3, "\n");
	amd76x_get_error_info(mci, &info);		amd76x_get_error_info(mci, &info);
	amd76x_process_error_info(mci, &info, 1);		amd76x_process_error_info(mci, &info, 1);
	}		}
	@@ -241,7 +241,7 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
	u32 ems_mode;		u32 ems_mode;
	struct amd76x_error_info discard;		struct amd76x_error_info discard;

	debugf0("\n");		edac_dbg(0, "\n");
	pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);		pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
	ems_mode = (ems >> 10) & 0x3;		ems_mode = (ems >> 10) & 0x3;

	@@ -256,7 +256,7 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
	if (mci == NULL)		if (mci == NULL)
	return -ENOMEM;		return -ENOMEM;

	debugf0("mci = %p\n", mci);		edac_dbg(0, "mci = %p\n", mci);
	mci->pdev = &pdev->dev;		mci->pdev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_RDDR;		mci->mtype_cap = MEM_FLAG_RDDR;
	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_EC \| EDAC_FLAG_SECDED;		mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_EC \| EDAC_FLAG_SECDED;
	@@ -276,7 +276,7 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
	* type of memory controller. The ID is therefore hardcoded to 0.		* type of memory controller. The ID is therefore hardcoded to 0.
	*/		*/
	if (edac_mc_add_mc(mci)) {		if (edac_mc_add_mc(mci)) {
	debugf3("failed edac_mc_add_mc()\n");		edac_dbg(3, "failed edac_mc_add_mc()\n");
	goto fail;		goto fail;
	}		}

	@@ -292,7 +292,7 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
	}		}

	/* get this far and it's successful */		/* get this far and it's successful */
	debugf3("success\n");		edac_dbg(3, "success\n");
	return 0;		return 0;

	fail:		fail:
	@@ -304,7 +304,7 @@ fail:
	static int __devinit amd76x_init_one(struct pci_dev *pdev,		static int __devinit amd76x_init_one(struct pci_dev *pdev,
	const struct pci_device_id *ent)		const struct pci_device_id *ent)
	{		{
	debugf0("\n");		edac_dbg(0, "\n");

	/* don't need to call pci_enable_device() */		/* don't need to call pci_enable_device() */
	return amd76x_probe1(pdev, ent->driver_data);		return amd76x_probe1(pdev, ent->driver_data);
	@@ -322,7 +322,7 @@ static void __devexit amd76x_remove_one(struct pci_dev *pdev)
	{		{
	struct mem_ctl_info *mci;		struct mem_ctl_info *mci;

	debugf0("\n");		edac_dbg(0, "\n");

	if (amd76x_pci)		if (amd76x_pci)
	edac_pci_release_generic_ctl(amd76x_pci);		edac_pci_release_generic_ctl(amd76x_pci);

drivers/edac/cpc925_edac.c

+11 −11

Original line number	Original line	Diff line number	Diff line
	@@ -316,12 +316,12 @@ static void get_total_mem(struct cpc925_mc_pdata *pdata)
	reg += aw;		reg += aw;
	size = of_read_number(reg, sw);		size = of_read_number(reg, sw);
	reg += sw;		reg += sw;
	debugf1("start 0x%lx, size 0x%lx\n", start, size);		edac_dbg(1, "start 0x%lx, size 0x%lx\n", start, size);
	pdata->total_mem += size;		pdata->total_mem += size;
	} while (reg < reg_end);		} while (reg < reg_end);

	of_node_put(np);		of_node_put(np);
	debugf0("total_mem 0x%lx\n", pdata->total_mem);		edac_dbg(0, "total_mem 0x%lx\n", pdata->total_mem);
	}		}

	static void cpc925_init_csrows(struct mem_ctl_info *mci)		static void cpc925_init_csrows(struct mem_ctl_info *mci)
	@@ -511,7 +511,7 @@ static void cpc925_mc_get_pfn(struct mem_ctl_info *mci, u32 mear,
	*offset = pa & (PAGE_SIZE - 1);		*offset = pa & (PAGE_SIZE - 1);
	*pfn = pa >> PAGE_SHIFT;		*pfn = pa >> PAGE_SHIFT;

	debugf0("ECC physical address 0x%lx\n", pa);		edac_dbg(0, "ECC physical address 0x%lx\n", pa);
	}		}

	static int cpc925_mc_find_channel(struct mem_ctl_info *mci, u16 syndrome)		static int cpc925_mc_find_channel(struct mem_ctl_info *mci, u16 syndrome)
	@@ -851,7 +851,7 @@ static void cpc925_add_edac_devices(void __iomem *vbase)
	goto err2;		goto err2;
	}		}

	debugf0("Successfully added edac device for %s\n",		edac_dbg(0, "Successfully added edac device for %s\n",
	dev_info->ctl_name);		dev_info->ctl_name);

	continue;		continue;
	@@ -883,7 +883,7 @@ static void cpc925_del_edac_devices(void)
	if (dev_info->exit)		if (dev_info->exit)
	dev_info->exit(dev_info);		dev_info->exit(dev_info);

	debugf0("Successfully deleted edac device for %s\n",		edac_dbg(0, "Successfully deleted edac device for %s\n",
	dev_info->ctl_name);		dev_info->ctl_name);
	}		}
	}		}
	@@ -899,7 +899,7 @@ static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci)
	mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET);		mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET);
	si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT;		si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT;

	debugf0("Mem Scrub Ctrl Register 0x%x\n", mscr);		edac_dbg(0, "Mem Scrub Ctrl Register 0x%x\n", mscr);

	if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) \|\|		if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) \|\|
	(si == 0)) {		(si == 0)) {
	@@ -927,7 +927,7 @@ static int cpc925_mc_get_channels(void __iomem *vbase)
	((mbcr & MBCR_64BITBUS_MASK) == 0))		((mbcr & MBCR_64BITBUS_MASK) == 0))
	dual = 1;		dual = 1;

	debugf0("%s channel\n", (dual > 0) ? "Dual" : "Single");		edac_dbg(0, "%s channel\n", (dual > 0) ? "Dual" : "Single");

	return dual;		return dual;
	}		}
	@@ -942,7 +942,7 @@ static int __devinit cpc925_probe(struct platform_device *pdev)
	struct resource *r;		struct resource *r;
	int res = 0, nr_channels;		int res = 0, nr_channels;

	debugf0("%s platform device found!\n", pdev->name);		edac_dbg(0, "%s platform device found!\n", pdev->name);

	if (!devres_open_group(&pdev->dev, cpc925_probe, GFP_KERNEL)) {		if (!devres_open_group(&pdev->dev, cpc925_probe, GFP_KERNEL)) {
	res = -ENOMEM;		res = -ENOMEM;
	@@ -1024,7 +1024,7 @@ static int __devinit cpc925_probe(struct platform_device *pdev)
	cpc925_add_edac_devices(vbase);		cpc925_add_edac_devices(vbase);

	/* get this far and it's successful */		/* get this far and it's successful */
	debugf0("success\n");		edac_dbg(0, "success\n");

	res = 0;		res = 0;
	goto out;		goto out;

drivers/edac/e752x_edac.c

+19 −20

Original line number	Original line	Diff line number	Diff line
	@@ -309,7 +309,7 @@ static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
	u32 remap;		u32 remap;
	struct e752x_pvt pvt = (struct e752x_pvt )mci->pvt_info;		struct e752x_pvt pvt = (struct e752x_pvt )mci->pvt_info;

	debugf3("\n");		edac_dbg(3, "\n");

	if (page < pvt->tolm)		if (page < pvt->tolm)
	return page;		return page;
	@@ -335,7 +335,7 @@ static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
	int i;		int i;
	struct e752x_pvt pvt = (struct e752x_pvt )mci->pvt_info;		struct e752x_pvt pvt = (struct e752x_pvt )mci->pvt_info;

	debugf3("\n");		edac_dbg(3, "\n");

	/* convert the addr to 4k page */		/* convert the addr to 4k page */
	page = sec1_add >> (PAGE_SHIFT - 4);		page = sec1_add >> (PAGE_SHIFT - 4);
	@@ -394,7 +394,7 @@ static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
	int row;		int row;
	struct e752x_pvt pvt = (struct e752x_pvt )mci->pvt_info;		struct e752x_pvt pvt = (struct e752x_pvt )mci->pvt_info;

	debugf3("\n");		edac_dbg(3, "\n");

	if (error_one & 0x0202) {		if (error_one & 0x0202) {
	error_2b = ded_add;		error_2b = ded_add;
	@@ -453,7 +453,7 @@ static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
	if (!handle_error)		if (!handle_error)
	return;		return;

	debugf3("\n");		edac_dbg(3, "\n");
	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0,		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0,
	-1, -1, -1,		-1, -1, -1,
	"e752x UE log memory write", "", NULL);		"e752x UE log memory write", "", NULL);
	@@ -982,7 +982,7 @@ static void e752x_check(struct mem_ctl_info *mci)
	{		{
	struct e752x_error_info info;		struct e752x_error_info info;

	debugf3("\n");		edac_dbg(3, "\n");
	e752x_get_error_info(mci, &info);		e752x_get_error_info(mci, &info);
	e752x_process_error_info(mci, &info, 1);		e752x_process_error_info(mci, &info, 1);
	}		}
	@@ -1102,8 +1102,7 @@ static void e752x_init_csrows(struct mem_ctl_info mci, struct pci_dev pdev,
	pci_read_config_byte(pdev, E752X_DRB + index, &value);		pci_read_config_byte(pdev, E752X_DRB + index, &value);
	/* convert a 128 or 64 MiB DRB to a page size. */		/* convert a 128 or 64 MiB DRB to a page size. */
	cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);		cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
	debugf3("(%d) cumul_size 0x%x\n", index,		edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
	cumul_size);
	if (cumul_size == last_cumul_size)		if (cumul_size == last_cumul_size)
	continue; /* not populated */		continue; /* not populated */

	@@ -1129,7 +1128,7 @@ static void e752x_init_csrows(struct mem_ctl_info mci, struct pci_dev pdev,
	for (i = 0; i < csrow->nr_channels; i++) {		for (i = 0; i < csrow->nr_channels; i++) {
	struct dimm_info *dimm = csrow->channels[i]->dimm;		struct dimm_info *dimm = csrow->channels[i]->dimm;

	debugf3("Initializing rank at (%i,%i)\n", index, i);		edac_dbg(3, "Initializing rank at (%i,%i)\n", index, i);
	dimm->nr_pages = nr_pages / csrow->nr_channels;		dimm->nr_pages = nr_pages / csrow->nr_channels;
	dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */		dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */
	dimm->mtype = MEM_RDDR; /* only one type supported */		dimm->mtype = MEM_RDDR; /* only one type supported */
	@@ -1270,8 +1269,8 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
	int drc_chan; /* Number of channels 0=1chan,1=2chan */		int drc_chan; /* Number of channels 0=1chan,1=2chan */
	struct e752x_error_info discard;		struct e752x_error_info discard;

	debugf0("mci\n");		edac_dbg(0, "mci\n");
	debugf0("Starting Probe1\n");		edac_dbg(0, "Starting Probe1\n");

	/* check to see if device 0 function 1 is enabled; if it isn't, we		/* check to see if device 0 function 1 is enabled; if it isn't, we
	* assume the BIOS has reserved it for a reason and is expecting		* assume the BIOS has reserved it for a reason and is expecting
	@@ -1301,7 +1300,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
	if (mci == NULL)		if (mci == NULL)
	return -ENOMEM;		return -ENOMEM;

	debugf3("init mci\n");		edac_dbg(3, "init mci\n");
	mci->mtype_cap = MEM_FLAG_RDDR;		mci->mtype_cap = MEM_FLAG_RDDR;
	/* 3100 IMCH supports SECDEC only */		/* 3100 IMCH supports SECDEC only */
	mci->edac_ctl_cap = (dev_idx == I3100) ? EDAC_FLAG_SECDED :		mci->edac_ctl_cap = (dev_idx == I3100) ? EDAC_FLAG_SECDED :
	@@ -1311,7 +1310,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
	mci->mod_ver = E752X_REVISION;		mci->mod_ver = E752X_REVISION;
	mci->pdev = &pdev->dev;		mci->pdev = &pdev->dev;

	debugf3("init pvt\n");		edac_dbg(3, "init pvt\n");
	pvt = (struct e752x_pvt *)mci->pvt_info;		pvt = (struct e752x_pvt *)mci->pvt_info;
	pvt->dev_info = &e752x_devs[dev_idx];		pvt->dev_info = &e752x_devs[dev_idx];
	pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);		pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
	@@ -1321,7 +1320,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
	return -ENODEV;		return -ENODEV;
	}		}

	debugf3("more mci init\n");		edac_dbg(3, "more mci init\n");
	mci->ctl_name = pvt->dev_info->ctl_name;		mci->ctl_name = pvt->dev_info->ctl_name;
	mci->dev_name = pci_name(pdev);		mci->dev_name = pci_name(pdev);
	mci->edac_check = e752x_check;		mci->edac_check = e752x_check;
	@@ -1343,7 +1342,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
	mci->edac_cap = EDAC_FLAG_SECDED; /* the only mode supported */		mci->edac_cap = EDAC_FLAG_SECDED; /* the only mode supported */
	else		else
	mci->edac_cap \|= EDAC_FLAG_NONE;		mci->edac_cap \|= EDAC_FLAG_NONE;
	debugf3("tolm, remapbase, remaplimit\n");		edac_dbg(3, "tolm, remapbase, remaplimit\n");

	/* load the top of low memory, remap base, and remap limit vars */		/* load the top of low memory, remap base, and remap limit vars */
	pci_read_config_word(pdev, E752X_TOLM, &pci_data);		pci_read_config_word(pdev, E752X_TOLM, &pci_data);
	@@ -1360,7 +1359,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
	* type of memory controller. The ID is therefore hardcoded to 0.		* type of memory controller. The ID is therefore hardcoded to 0.
	*/		*/
	if (edac_mc_add_mc(mci)) {		if (edac_mc_add_mc(mci)) {
	debugf3("failed edac_mc_add_mc()\n");		edac_dbg(3, "failed edac_mc_add_mc()\n");
	goto fail;		goto fail;
	}		}

	@@ -1378,7 +1377,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
	}		}

	/* get this far and it's successful */		/* get this far and it's successful */
	debugf3("success\n");		edac_dbg(3, "success\n");
	return 0;		return 0;

	fail:		fail:
	@@ -1394,7 +1393,7 @@ fail:
	static int __devinit e752x_init_one(struct pci_dev *pdev,		static int __devinit e752x_init_one(struct pci_dev *pdev,
	const struct pci_device_id *ent)		const struct pci_device_id *ent)
	{		{
	debugf0("\n");		edac_dbg(0, "\n");

	/* wake up and enable device */		/* wake up and enable device */
	if (pci_enable_device(pdev) < 0)		if (pci_enable_device(pdev) < 0)
	@@ -1408,7 +1407,7 @@ static void __devexit e752x_remove_one(struct pci_dev *pdev)
	struct mem_ctl_info *mci;		struct mem_ctl_info *mci;
	struct e752x_pvt *pvt;		struct e752x_pvt *pvt;

	debugf0("\n");		edac_dbg(0, "\n");

	if (e752x_pci)		if (e752x_pci)
	edac_pci_release_generic_ctl(e752x_pci);		edac_pci_release_generic_ctl(e752x_pci);
	@@ -1454,7 +1453,7 @@ static int __init e752x_init(void)
	{		{
	int pci_rc;		int pci_rc;

	debugf3("\n");		edac_dbg(3, "\n");

	/* Ensure that the OPSTATE is set correctly for POLL or NMI */		/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	opstate_init();		opstate_init();
	@@ -1465,7 +1464,7 @@ static int __init e752x_init(void)

	static void __exit e752x_exit(void)		static void __exit e752x_exit(void)
	{		{
	debugf3("\n");		edac_dbg(3, "\n");
	pci_unregister_driver(&e752x_driver);		pci_unregister_driver(&e752x_driver);
	}		}