Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 94bd3279 authored by Alexander Shiyan's avatar Alexander Shiyan Committed by Arnd Bergmann
Browse files

ARM: clps711x: Combine header files into one for clps711x-targets 



Current ARM7 Cirrus Logic product line contains only 3 cpu.
EP7312 - Fully functional.
EP7309 - Missing SDRAM interface.
EP7311 - Missing DAI.
It makes no sense to separate the header files to identify these differences,
it is only necessary to keep in mind the presence or lack of any features of
a specific CPU when writing code.

Signed-off-by: default avatarAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 304b2c68

arch/arm/include/asm/hardware/clps7111.h

+59 −0
Original line number Diff line number Diff line
@@ -27,9 +27,11 @@ 


#define PADR		(0x0000)

#define PBDR		(0x0001)

#define PCDR		(0x0002)

#define PDDR		(0x0003)

#define PADDR		(0x0040)

#define PBDDR		(0x0041)

#define PCDDR		(0x0042)

#define PDDDR		(0x0043)

#define PEDR		(0x0080)

#define PEDDR		(0x00c0)
@@ -76,6 +78,18 @@ 
#define SS2POP		(0x16c0)

#define KBDEOI		(0x1700)



#define DAIR		(0x2000)

#define DAIR0		(0x2040)

#define DAIDR1		(0x2080)

#define DAIDR2		(0x20c0)

#define DAISR		(0x2100)

#define SYSCON3		(0x2200)

#define INTSR3		(0x2240)

#define INTMR3		(0x2280)

#define LEDFLSH		(0x22c0)

#define SDCONF		(0x2300)

#define SDRFPR		(0x2340)



/* common bits: SYSCON1 / SYSCON2 */

#define SYSCON_UARTEN		(1 << 8)
@@ -172,4 +186,49 @@ 
#define SYNCIO_SMCKEN		(1 << 13)

#define SYNCIO_TXFRMEN		(1 << 14)



#define DAIR_DAIEN		(1 << 16)

#define DAIR_ECS		(1 << 17)

#define DAIR_LCTM		(1 << 19)

#define DAIR_LCRM		(1 << 20)

#define DAIR_RCTM		(1 << 21)

#define DAIR_RCRM		(1 << 22)

#define DAIR_LBM		(1 << 23)



#define DAIDR2_FIFOEN		(1 << 15)

#define DAIDR2_FIFOLEFT		(0x0d << 16)

#define DAIDR2_FIFORIGHT	(0x11 << 16)



#define DAISR_RCTS		(1 << 0)

#define DAISR_RCRS		(1 << 1)

#define DAISR_LCTS		(1 << 2)

#define DAISR_LCRS		(1 << 3)

#define DAISR_RCTU		(1 << 4)

#define DAISR_RCRO		(1 << 5)

#define DAISR_LCTU		(1 << 6)

#define DAISR_LCRO		(1 << 7)

#define DAISR_RCNF		(1 << 8)

#define DAISR_RCNE		(1 << 9)

#define DAISR_LCNF		(1 << 10)

#define DAISR_LCNE		(1 << 11)

#define DAISR_FIFO		(1 << 12)



#define SYSCON3_ADCCON		(1 << 0)

#define SYSCON3_DAISEL		(1 << 3)

#define SYSCON3_ADCCKNSEN	(1 << 4)

#define SYSCON3_FASTWAKE	(1 << 8)

#define SYSCON3_DAIEN		(1 << 9)



#define SDCONF_ACTIVE		(1 << 10)

#define SDCONF_CLKCTL		(1 << 9)

#define SDCONF_WIDTH_4		(0 << 7)

#define SDCONF_WIDTH_8		(1 << 7)

#define SDCONF_WIDTH_16		(2 << 7)

#define SDCONF_WIDTH_32		(3 << 7)

#define SDCONF_SIZE_16		(0 << 5)

#define SDCONF_SIZE_64		(1 << 5)

#define SDCONF_SIZE_128		(2 << 5)

#define SDCONF_SIZE_256		(3 << 5)

#define SDCONF_CASLAT_2		(2)

#define SDCONF_CASLAT_3		(3)



#endif /* __ASM_HARDWARE_CLPS7111_H */

arch/arm/include/asm/hardware/cs89712.h

deleted100644 → 0
+0 −49
Original line number Diff line number Diff line 
/*

 *  arch/arm/include/asm/hardware/cs89712.h

 *

 *  This file contains the hardware definitions of the CS89712

 *  additional internal registers.

 *

 *  Copyright (C) 2001 Thomas Gleixner autronix automation <gleixner@autronix.de>

 *			

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#ifndef __ASM_HARDWARE_CS89712_H

#define __ASM_HARDWARE_CS89712_H



/*

*	CS89712 additional registers

*/

                                  

#define PCDR			0x0002	/* Port C Data register ---------------------------- */

#define PCDDR			0x0042	/* Port C Data Direction register ------------------ */

#define SDCONF			0x2300  /* SDRAM Configuration register ---------------------*/

#define SDRFPR			0x2340  /* SDRAM Refresh period register --------------------*/



#define SDCONF_ACTIVE		(1 << 10)

#define SDCONF_CLKCTL		(1 << 9)

#define SDCONF_WIDTH_4		(0 << 7)

#define SDCONF_WIDTH_8		(1 << 7)

#define SDCONF_WIDTH_16		(2 << 7)

#define SDCONF_WIDTH_32		(3 << 7)

#define SDCONF_SIZE_16		(0 << 5)

#define SDCONF_SIZE_64		(1 << 5)

#define SDCONF_SIZE_128		(2 << 5)

#define SDCONF_SIZE_256		(3 << 5)

#define SDCONF_CASLAT_2		(2)

#define SDCONF_CASLAT_3		(3)



#endif /* __ASM_HARDWARE_CS89712_H */

arch/arm/include/asm/hardware/ep7211.h

deleted100644 → 0
+0 −31
Original line number Diff line number Diff line 
/*

 *  arch/arm/include/asm/hardware/ep7211.h

 *

 *  This file contains the hardware definitions of the EP7211 internal

 *  registers.

 *

 *  Copyright (C) 2001 Blue Mug, Inc.  All Rights Reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#ifndef __ASM_HARDWARE_EP7211_H

#define __ASM_HARDWARE_EP7211_H



/*

 * XXX miket@bluemug.com: need to introduce EP7211 registers (those not

 * present in 7212) here.

 */



#endif /* __ASM_HARDWARE_EP7211_H */

arch/arm/include/asm/hardware/ep7212.h

deleted100644 → 0
+0 −71
Original line number Diff line number Diff line 
/*

 *  arch/arm/include/asm/hardware/ep7212.h

 *

 *  This file contains the hardware definitions of the EP7212 internal

 *  registers.

 *

 *  Copyright (C) 2000 Deep Blue Solutions Ltd.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#ifndef __ASM_HARDWARE_EP7212_H

#define __ASM_HARDWARE_EP7212_H



/*

 * These registers are specific to the EP7212 only

 */

#define DAIR			0x2000

#define DAIR0			0x2040

#define DAIDR1			0x2080

#define DAIDR2			0x20c0

#define DAISR			0x2100

#define SYSCON3			0x2200

#define INTSR3			0x2240

#define INTMR3			0x2280

#define LEDFLSH			0x22c0



#define DAIR_DAIEN		(1 << 16)

#define DAIR_ECS		(1 << 17)

#define DAIR_LCTM		(1 << 19)

#define DAIR_LCRM		(1 << 20)

#define DAIR_RCTM		(1 << 21)

#define DAIR_RCRM		(1 << 22)

#define DAIR_LBM		(1 << 23)



#define DAIDR2_FIFOEN		(1 << 15)

#define DAIDR2_FIFOLEFT		(0x0d << 16)

#define DAIDR2_FIFORIGHT	(0x11 << 16)



#define DAISR_RCTS		(1 << 0)

#define DAISR_RCRS		(1 << 1)

#define DAISR_LCTS		(1 << 2)

#define DAISR_LCRS		(1 << 3)

#define DAISR_RCTU		(1 << 4)

#define DAISR_RCRO		(1 << 5)

#define DAISR_LCTU		(1 << 6)

#define DAISR_LCRO		(1 << 7)

#define DAISR_RCNF		(1 << 8)

#define DAISR_RCNE		(1 << 9)

#define DAISR_LCNF		(1 << 10)

#define DAISR_LCNE		(1 << 11)

#define DAISR_FIFO		(1 << 12)



#define SYSCON3_ADCCON		(1 << 0)

#define SYSCON3_DAISEL		(1 << 3)

#define SYSCON3_ADCCKNSEN	(1 << 4)

#define SYSCON3_FASTWAKE	(1 << 8)

#define SYSCON3_DAIEN		(1 << 9)



#endif /* __ASM_HARDWARE_EP7212_H */

arch/arm/mach-clps711x/Kconfig

+4 −17
Original line number Diff line number Diff line 
if ARCH_CLPS711X



menu "CLPS711X/EP721X Implementations"

menu "CLPS711X/EP721X/EP731X Implementations"



config ARCH_AUTCPU12

	bool "AUTCPU12"
@@ -45,26 +45,13 @@ config ARCH_P720T 
config ARCH_FORTUNET

	bool "FORTUNET"



# XXX Maybe these should indicate register compatibility

# instead of being mutually exclusive.

config ARCH_EP7211

	bool

	depends on ARCH_EDB7211

	default y



config ARCH_EP7212

	bool

	depends on ARCH_P720T || ARCH_CEIVA

	default y



config EP72XX_ROM_BOOT

	bool "EP72xx ROM boot"

	depends on ARCH_EP7211 || ARCH_EP7212

	---help---

	bool "EP721x/EP731x ROM boot"

	help

	  If you say Y here, your CLPS711x-based kernel will use the bootstrap

	  mode memory map instead of the normal memory map.



	  Processors derived from the Cirrus CLPS-711X core support two boot

	  Processors derived from the Cirrus CLPS711X core support two boot

	  modes.  Normal mode boots from the external memory device at CS0.

	  Bootstrap mode rearranges parts of the memory map, placing an

	  internal 128 byte bootstrap ROM at CS0.  This option performs the