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Commit 93dd7f48 authored by Viswanadha Raju Thotakura's avatar Viswanadha Raju Thotakura Committed by Kyle Yan
Browse files

ARM: dts: msm: Add missing clocks for csid on msmcobalt 



Add missing clocks for csid node. Update csiphytimer clock
to 269MHz.

CRs-Fixed: 1021009
Change-Id: I9242849d4da84007d1384de0e3e2bf63e7f57ea9
Signed-off-by: default avatarViswanadha Raju Thotakura <viswanad@codeaurora.org>
parent 42ab5394

arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi

+27 −15
Original line number Diff line number Diff line
@@ -48,7 +48,7 @@ 
			"csi_src_clk", "csi_clk", "cphy_csid_clk",

			"csiphy_timer_src_clk", "csiphy_timer_clk",

			"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";

		qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0

		qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0

			0 256000000 0>;

	};
@@ -79,7 +79,7 @@ 
			"csi_src_clk", "csi_clk", "cphy_csid_clk",

			"csiphy_timer_src_clk", "csiphy_timer_clk",

			"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";

		qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0

		qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0

			0 256000000 0>;

	};
@@ -110,7 +110,7 @@ 
			"csi_src_clk", "csi_clk", "cphy_csid_clk",

			"csiphy_timer_src_clk", "csiphy_timer_clk",

			"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";

		qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0

		qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0

			0 256000000 0>;

	};
@@ -138,14 +138,17 @@ 
			<&clock_mmss clk_mmss_camss_csiphy0_clk>,

			<&clock_mmss clk_mmss_camss_csi0_ahb_clk>,

			<&clock_mmss clk_mmss_camss_csi0rdi_clk>,

			<&clock_mmss clk_mmss_camss_csi0pix_clk>;

			<&clock_mmss clk_mmss_camss_csi0pix_clk>,

			<&clock_mmss clk_mmss_camss_cphy_csid0_clk>,

			<&clock_mmss clk_csiphy_clk_src>;

		clock-names = "mnoc_maxi", "mnoc_ahb",

			"bmic_smmu_ahb", "bmic_smmu_axi",

			"camss_ahb_clk", "camss_top_ahb_clk",

			"ispif_ahb_clk", "csi_src_clk", "csi_clk",

			"csi_phy_clk", "csi_ahb_clk", "csi_rdi_clk",

			"csi_pix_clk";

		qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0 0>;

			"csi_pix_clk", "cphy_csid_clk", "cphy_clk_src";

		qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0 0 0

			256000000>;

		status = "ok";

	};
@@ -173,14 +176,17 @@ 
			<&clock_mmss clk_mmss_camss_csiphy1_clk>,

			<&clock_mmss clk_mmss_camss_csi1_ahb_clk>,

			<&clock_mmss clk_mmss_camss_csi1rdi_clk>,

			<&clock_mmss clk_mmss_camss_csi1pix_clk>;

			<&clock_mmss clk_mmss_camss_csi1pix_clk>,

			<&clock_mmss clk_mmss_camss_cphy_csid1_clk>,

			<&clock_mmss clk_csiphy_clk_src>;

		clock-names = "mnoc_maxi", "mnoc_ahb",

			"bmic_smmu_ahb", "bmic_smmu_axi",

			"camss_ahb_clk", "camss_top_ahb_clk",

			"ispif_ahb_clk", "csi_src_clk", "csi_clk",

			"csi_phy_clk", "csi_ahb_clk", "csi_rdi_clk",

			"csi_pix_clk";

		qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0 0>;

			"csi_pix_clk", "cphy_csid_clk", "cphy_clk_src";

		qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0 0 0

			256000000>;

	};



	qcom,csid@ca30800 {
@@ -207,14 +213,17 @@ 
			<&clock_mmss clk_mmss_camss_csiphy2_clk>,

			<&clock_mmss clk_mmss_camss_csi2_ahb_clk>,

			<&clock_mmss clk_mmss_camss_csi2rdi_clk>,

			<&clock_mmss clk_mmss_camss_csi2pix_clk>;

			<&clock_mmss clk_mmss_camss_csi2pix_clk>,

			<&clock_mmss clk_mmss_camss_cphy_csid2_clk>,

			<&clock_mmss clk_csiphy_clk_src>;

		clock-names = "mnoc_maxi", "mnoc_ahb",

			"bmic_smmu_ahb", "bmic_smmu_axi",

			"camss_ahb_clk", "camss_top_ahb_clk",

			"ispif_ahb_clk", "csi_src_clk", "csi_clk",

			"csi_phy_clk", "csi_ahb_clk", "csi_rdi_clk",

			"csi_pix_clk";

		qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0 0>;

			"csi_pix_clk", "cphy_csid_clk", "cphy_clk_src";

		qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0 0 0

			256000000>;

	};



	qcom,csid@ca30c00 {
@@ -240,14 +249,17 @@ 
			<&clock_mmss clk_mmss_camss_csi3_clk>,

			<&clock_mmss clk_mmss_camss_csi3_ahb_clk>,

			<&clock_mmss clk_mmss_camss_csi3rdi_clk>,

			<&clock_mmss clk_mmss_camss_csi3pix_clk>;

			<&clock_mmss clk_mmss_camss_csi3pix_clk>,

			<&clock_mmss clk_mmss_camss_cphy_csid1_clk>,

			<&clock_mmss clk_csiphy_clk_src>;

		clock-names = "mnoc_maxi", "mnoc_ahb",

			"bmic_smmu_ahb", "bmic_smmu_axi",

			"camss_ahb_clk", "camss_top_ahb_clk",

			"ispif_ahb_clk", "csi_src_clk", "csi_clk",

			"csi_ahb_clk", "csi_rdi_clk",

			"csi_pix_clk";

		qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0>;

			"csi_pix_clk", "cphy_csid_clk", "cphy_clk_src";

		qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0 0

			256000000>;

	};

	qcom,cam_smmu {

		compatible = "qcom,msm-cam-smmu";