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Commit 912a2bfd authored by Siddhartha Agrawal's avatar Siddhartha Agrawal
Browse files

msm: mdss: dsi: Configure pll to work only in full rate mode 



Update the DSI phy v3 initialization sequence as per the
recommended values. The key changes include changing the operating
mode from hybrid to full-rate only.

Change-Id: I999c6f2f76b8991172cd2f5c4b6c99e0ed5d186b
Signed-off-by: default avatarSiddhartha Agrawal <agrawals@codeaurora.org>
parent ab26d098

drivers/video/fbdev/msm/mdss_dsi_phy_v3.c

+3 −3
Original line number Diff line number Diff line
@@ -183,7 +183,7 @@ static void mdss_dsi_phy_v3_config_lane_settings( 
	struct mdss_dsi_ctrl_pdata *ctrl)

{

	int i;

	u32 tx_dctrl[] = {0x18, 0x19, 0x18, 0x02, 0x18};

	u32 tx_dctrl[] = {0x00, 0x00, 0x00, 0x02, 0x01};

	struct mdss_dsi_phy_ctrl *pd =

		&(((ctrl->panel_data).panel_info.mipi).dsi_phy_db);
@@ -407,8 +407,8 @@ int mdss_dsi_phy_v3_init(struct mdss_dsi_ctrl_pdata *ctrl, 


	mdss_dsi_phy_v3_lanes_enable(ctrl);



	/* Select hybrid mode and use local-wordclk */

	DSI_PHY_W32(ctrl->phy_io.base, CMN_CTRL_2, 0x08);

	/* Select full-rate mode */

	DSI_PHY_W32(ctrl->phy_io.base, CMN_CTRL_2, 0x40);



	mdss_dsi_phy_v3_set_pll_source(ctrl);