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Commit 8c2d0be7 authored by Alexander Graf's avatar Alexander Graf
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KVM: PPC: Book3S: PR: Optimize entry path 



By shuffling a few instructions around we can execute more memory
loads in parallel, giving us a small performance boost.

With this patch and a simple priviledged SPR access loop guest, I get
a speed bump from 2013052 to 2035607 exits per second.

Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
parent 30124906

arch/powerpc/kvm/book3s_segment.S

+7 −6
Original line number Original line Diff line number Diff line
@@ -128,24 +128,25 @@ no_dcbz32_on: 
	/* First clear RI in our current MSR value */

	/* First clear RI in our current MSR value */

	li	r0, MSR_RI

	li	r0, MSR_RI

	andc	r6, r6, r0

	andc	r6, r6, r0

	MTMSR_EERI(r6)

	mtsrr0	r9

	mtsrr1	r4





	PPC_LL	r0, SVCPU_R0(r3)

	PPC_LL	r0, SVCPU_R0(r3)

	PPC_LL	r1, SVCPU_R1(r3)

	PPC_LL	r1, SVCPU_R1(r3)

	PPC_LL	r2, SVCPU_R2(r3)

	PPC_LL	r2, SVCPU_R2(r3)

	PPC_LL	r4, SVCPU_R4(r3)

	PPC_LL	r5, SVCPU_R5(r3)

	PPC_LL	r5, SVCPU_R5(r3)

	PPC_LL	r6, SVCPU_R6(r3)

	PPC_LL	r7, SVCPU_R7(r3)

	PPC_LL	r7, SVCPU_R7(r3)

	PPC_LL	r8, SVCPU_R8(r3)

	PPC_LL	r8, SVCPU_R8(r3)

	PPC_LL	r9, SVCPU_R9(r3)

	PPC_LL	r10, SVCPU_R10(r3)

	PPC_LL	r10, SVCPU_R10(r3)

	PPC_LL	r11, SVCPU_R11(r3)

	PPC_LL	r11, SVCPU_R11(r3)

	PPC_LL	r12, SVCPU_R12(r3)

	PPC_LL	r12, SVCPU_R12(r3)

	PPC_LL	r13, SVCPU_R13(r3)

	PPC_LL	r13, SVCPU_R13(r3)





	MTMSR_EERI(r6)

	mtsrr0	r9

	mtsrr1	r4



	PPC_LL	r4, SVCPU_R4(r3)

	PPC_LL	r6, SVCPU_R6(r3)

	PPC_LL	r9, SVCPU_R9(r3)

	PPC_LL	r3, (SVCPU_R3)(r3)

	PPC_LL	r3, (SVCPU_R3)(r3)





	RFI

	RFI