Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 897de50e authored by Borislav Petkov's avatar Borislav Petkov Committed by H. Peter Anvin
Browse files

x86, cacheinfo: Add cache index disable sysfs attrs only to L3 caches 



The cache_disable_[01] attribute in

/sys/devices/system/cpu/cpu?/cache/index[0-3]/

is enabled on all cache levels although only L3 supports it. Add it only
to the cache level that actually supports it.

Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <1264172467-25155-5-git-send-email-bp@amd64.org>
Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent dcf39daf

arch/x86/kernel/cpu/intel_cacheinfo.c

+26 −9
Original line number Diff line number Diff line
@@ -814,16 +814,24 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644, 
static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,

		show_cache_disable_1, store_cache_disable_1);



#define DEFAULT_SYSFS_CACHE_ATTRS	\

	&type.attr,			\

	&level.attr,			\

	&coherency_line_size.attr,	\

	&physical_line_partition.attr,	\

	&ways_of_associativity.attr,	\

	&number_of_sets.attr,		\

	&size.attr,			\

	&shared_cpu_map.attr,		\

	&shared_cpu_list.attr



static struct attribute *default_attrs[] = {

	&type.attr,

	&level.attr,

	&coherency_line_size.attr,

	&physical_line_partition.attr,

	&ways_of_associativity.attr,

	&number_of_sets.attr,

	&size.attr,

	&shared_cpu_map.attr,

	&shared_cpu_list.attr,

	DEFAULT_SYSFS_CACHE_ATTRS,

	NULL

};



static struct attribute *default_l3_attrs[] = {

	DEFAULT_SYSFS_CACHE_ATTRS,

	&cache_disable_0.attr,

	&cache_disable_1.attr,

	NULL
@@ -916,6 +924,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev) 
	unsigned int cpu = sys_dev->id;

	unsigned long i, j;

	struct _index_kobject *this_object;

	struct _cpuid4_info   *this_leaf;

	int retval;



	retval = cpuid4_cache_sysfs_init(cpu);
@@ -934,6 +943,14 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev) 
		this_object = INDEX_KOBJECT_PTR(cpu, i);

		this_object->cpu = cpu;

		this_object->index = i;



		this_leaf = CPUID4_INFO_IDX(cpu, i);



		if (this_leaf->can_disable)

			ktype_cache.default_attrs = default_l3_attrs;

		else

			ktype_cache.default_attrs = default_attrs;



		retval = kobject_init_and_add(&(this_object->kobj),

					      &ktype_cache,

					      per_cpu(ici_cache_kobject, cpu),