Loading drivers/clk/msm/clock-gcc-cobalt.c +1 −15 Original line number Diff line number Diff line Loading @@ -1698,19 +1698,6 @@ static struct branch_clk gcc_gpu_iref_clk = { }, }; static struct local_vote_clk gcc_bimc_hmss_axi_clk = { .cbcr_reg = GCC_BIMC_HMSS_AXI_CBCR, .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE, .en_mask = BIT(22), .base = &virt_base, .c = { .dbg_name = "gcc_bimc_hmss_axi_clk", .always_on = true, .ops = &clk_ops_vote, CLK_INIT(gcc_bimc_hmss_axi_clk.c), }, }; static struct local_vote_clk gcc_hmss_ahb_clk = { .cbcr_reg = GCC_HMSS_AHB_CBCR, .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE, Loading Loading @@ -2439,7 +2426,7 @@ static struct mux_clk gcc_debug_mux = { { &ce1_clk.c, 0x0097 }, { &gcc_ce1_axi_m_clk.c, 0x0098 }, { &gcc_ce1_ahb_m_clk.c, 0x0099 }, { &gcc_bimc_hmss_axi_clk.c, 0x00bb }, { &measure_only_bimc_hmss_axi_clk.c, 0x00bb }, { &gcc_bimc_gfx_clk.c, 0x00ac }, { &gcc_hmss_ahb_clk.c, 0x00ba }, { &gcc_hmss_rbcpr_clk.c, 0x00bc }, Loading Loading @@ -2661,7 +2648,6 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { CLK_LIST(gcc_gpu_cfg_ahb_clk), CLK_LIST(gcc_gpu_snoc_dvm_gfx_clk), CLK_LIST(gcc_gpu_iref_clk), CLK_LIST(gcc_bimc_hmss_axi_clk), CLK_LIST(gcc_hmss_ahb_clk), CLK_LIST(gcc_hmss_dvm_bus_clk), CLK_LIST(gcc_hmss_rbcpr_clk), Loading include/dt-bindings/clock/msm-clocks-cobalt.h +0 −1 Original line number Diff line number Diff line Loading @@ -197,7 +197,6 @@ #define clk_gcc_gpu_snoc_dvm_gfx_clk 0xc9147451 #define clk_gcc_gpu_bimc_gfx_clk 0x3909459b #define clk_gcc_gpu_bimc_gfx_src_clk 0x377cb748 #define clk_gcc_bimc_hmss_axi_clk 0x84653931 #define clk_gcc_gpu_cfg_ahb_clk 0x72f20a57 #define clk_gcc_gpu_iref_clk 0xfd82abad #define clk_gcc_hmss_ahb_clk 0x62818713 Loading include/dt-bindings/clock/msm-clocks-hwio-cobalt.h +0 −1 Original line number Diff line number Diff line Loading @@ -171,7 +171,6 @@ #define GCC_GPU_CFG_AHB_CBCR 0x71004 #define GCC_GPU_SNOC_DVM_GFX_CBCR 0x71018 #define GCC_GPU_IREF_EN 0x88010 #define GCC_BIMC_HMSS_AXI_CBCR 0x48004 #define GCC_HMSS_AHB_CBCR 0x48000 #define GCC_HMSS_DVM_BUS_CBCR 0x4808C #define GCC_HMSS_RBCPR_CBCR 0x48008 Loading Loading
drivers/clk/msm/clock-gcc-cobalt.c +1 −15 Original line number Diff line number Diff line Loading @@ -1698,19 +1698,6 @@ static struct branch_clk gcc_gpu_iref_clk = { }, }; static struct local_vote_clk gcc_bimc_hmss_axi_clk = { .cbcr_reg = GCC_BIMC_HMSS_AXI_CBCR, .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE, .en_mask = BIT(22), .base = &virt_base, .c = { .dbg_name = "gcc_bimc_hmss_axi_clk", .always_on = true, .ops = &clk_ops_vote, CLK_INIT(gcc_bimc_hmss_axi_clk.c), }, }; static struct local_vote_clk gcc_hmss_ahb_clk = { .cbcr_reg = GCC_HMSS_AHB_CBCR, .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE, Loading Loading @@ -2439,7 +2426,7 @@ static struct mux_clk gcc_debug_mux = { { &ce1_clk.c, 0x0097 }, { &gcc_ce1_axi_m_clk.c, 0x0098 }, { &gcc_ce1_ahb_m_clk.c, 0x0099 }, { &gcc_bimc_hmss_axi_clk.c, 0x00bb }, { &measure_only_bimc_hmss_axi_clk.c, 0x00bb }, { &gcc_bimc_gfx_clk.c, 0x00ac }, { &gcc_hmss_ahb_clk.c, 0x00ba }, { &gcc_hmss_rbcpr_clk.c, 0x00bc }, Loading Loading @@ -2661,7 +2648,6 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { CLK_LIST(gcc_gpu_cfg_ahb_clk), CLK_LIST(gcc_gpu_snoc_dvm_gfx_clk), CLK_LIST(gcc_gpu_iref_clk), CLK_LIST(gcc_bimc_hmss_axi_clk), CLK_LIST(gcc_hmss_ahb_clk), CLK_LIST(gcc_hmss_dvm_bus_clk), CLK_LIST(gcc_hmss_rbcpr_clk), Loading
include/dt-bindings/clock/msm-clocks-cobalt.h +0 −1 Original line number Diff line number Diff line Loading @@ -197,7 +197,6 @@ #define clk_gcc_gpu_snoc_dvm_gfx_clk 0xc9147451 #define clk_gcc_gpu_bimc_gfx_clk 0x3909459b #define clk_gcc_gpu_bimc_gfx_src_clk 0x377cb748 #define clk_gcc_bimc_hmss_axi_clk 0x84653931 #define clk_gcc_gpu_cfg_ahb_clk 0x72f20a57 #define clk_gcc_gpu_iref_clk 0xfd82abad #define clk_gcc_hmss_ahb_clk 0x62818713 Loading
include/dt-bindings/clock/msm-clocks-hwio-cobalt.h +0 −1 Original line number Diff line number Diff line Loading @@ -171,7 +171,6 @@ #define GCC_GPU_CFG_AHB_CBCR 0x71004 #define GCC_GPU_SNOC_DVM_GFX_CBCR 0x71018 #define GCC_GPU_IREF_EN 0x88010 #define GCC_BIMC_HMSS_AXI_CBCR 0x48004 #define GCC_HMSS_AHB_CBCR 0x48000 #define GCC_HMSS_DVM_BUS_CBCR 0x4808C #define GCC_HMSS_RBCPR_CBCR 0x48008 Loading