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Commit 85700def authored by Chandan Uddaraju's avatar Chandan Uddaraju
Browse files

mdss: display-port: add support to configure stream attributes 



Update the MISC settings register according the color
depth and format. Update the MVID and NVID registers
using the M and N values used to configuring
the DP pixel clock.

Change-Id: I67e08d3491fbb7c0960c463cc8f979238b89d818
Signed-off-by: default avatarChandan Uddaraju <chandanu@codeaurora.org>
parent 0659e585

arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -468,9 +468,10 @@ 
		reg =	<0xc990000 0xa84>,

			<0xc011000 0x910>,

			<0x1fcb200 0x050>,

			<0xc8c2200 0x1a0>,

			<0x780000 0x621c>,

			<0xc9e1000 0x02c>;

		reg-names = "dp_ctrl", "dp_phy", "tcsr_regs",

		reg-names = "dp_ctrl", "dp_phy", "tcsr_regs", "dp_mmss_cc",

				"qfprom_physical","hdcp_physical";



		clocks = <&clock_mmss clk_mmss_mnoc_ahb_clk>,

drivers/video/fbdev/msm/mdss_dp.c

+7 −1
Original line number Diff line number Diff line
@@ -1133,7 +1133,7 @@ static void mdss_dp_configure_source_params(struct mdss_dp_drv_pdata *dp, 
	mdss_dp_fill_link_cfg(dp);

	mdss_dp_mainlink_ctrl(&dp->ctrl_io, true);

	mdss_dp_config_ctrl(dp);

	mdss_dp_sw_mvid_nvid(&dp->ctrl_io);

	mdss_dp_sw_config_msa(&dp->ctrl_io, dp->link_rate, &dp->dp_cc_io);

	mdss_dp_timing_cfg(&dp->ctrl_io, &dp->panel_data.panel_info);

}
@@ -2041,6 +2041,12 @@ static int mdss_retrieve_dp_ctrl_resources(struct platform_device *pdev, 
		return rc;

	}



	if (msm_dss_ioremap_byname(pdev, &dp_drv->dp_cc_io, "dp_mmss_cc")) {

		pr_err("%d unable to remap dp MMSS_CC resources\n",

				__LINE__);

		return rc;

	}



	if (msm_dss_ioremap_byname(pdev, &dp_drv->qfprom_io,

					"qfprom_physical"))

		pr_warn("unable to remap dp qfprom resources\n");

drivers/video/fbdev/msm/mdss_dp.h

+1 −0
Original line number Diff line number Diff line
@@ -406,6 +406,7 @@ struct mdss_dp_drv_pdata { 
	struct dss_io_data ctrl_io;

	struct dss_io_data phy_io;

	struct dss_io_data tcsr_reg_io;

	struct dss_io_data dp_cc_io;

	struct dss_io_data qfprom_io;

	struct dss_io_data hdcp_io;

	int base_size;

drivers/video/fbdev/msm/mdss_dp_aux.c

+2 −0
Original line number Diff line number Diff line
@@ -1647,6 +1647,8 @@ int mdss_dp_link_train(struct mdss_dp_drv_pdata *dp) 
clear:

	dp_clear_training_pattern(dp);

	if (ret != -EINVAL) {

		mdss_dp_config_misc_settings(&dp->ctrl_io,

				&dp->panel_data.panel_info);

		mdss_dp_setup_tr_unit(&dp->ctrl_io, dp->link_rate,

					dp->lane_cnt, dp->vic);

		mdss_dp_state_ctrl(&dp->ctrl_io, ST_SEND_VIDEO);

drivers/video/fbdev/msm/mdss_dp_util.c

+41 −5
Original line number Diff line number Diff line
@@ -253,10 +253,48 @@ void mdss_dp_timing_cfg(struct dss_io_data *ctrl_io, 
	writel_relaxed(data, ctrl_io->base + DP_ACTIVE_HOR_VER);

}



void mdss_dp_sw_mvid_nvid(struct dss_io_data *ctrl_io)

void mdss_dp_sw_config_msa(struct dss_io_data *ctrl_io,

				char lrate, struct dss_io_data *dp_cc_io)

{

	writel_relaxed(0x37, ctrl_io->base + DP_SOFTWARE_MVID);

	writel_relaxed(0x3c, ctrl_io->base + DP_SOFTWARE_NVID);

	u32 pixel_m, pixel_n;

	u32 mvid, nvid;



	pixel_m = readl_relaxed(dp_cc_io->base + MMSS_DP_PIXEL_M);

	pixel_n = readl_relaxed(dp_cc_io->base + MMSS_DP_PIXEL_N);

	pr_debug("pixel_m=0x%x, pixel_n=0x%x\n",

					pixel_m, pixel_n);



	mvid = (pixel_m & 0xFFFF) * 5;

	nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF);

	if (lrate == DP_LINK_RATE_540)

		nvid = nvid * 2;

	pr_debug("mvid=0x%x, nvid=0x%x\n", mvid, nvid);

	writel_relaxed(mvid, ctrl_io->base + DP_SOFTWARE_MVID);

	writel_relaxed(nvid, ctrl_io->base + DP_SOFTWARE_NVID);

}



void mdss_dp_config_misc_settings(struct dss_io_data *ctrl_io,

					struct mdss_panel_info *pinfo)

{

	u32 bpp = pinfo->bpp;

	u32 misc_val = 0x0;



	switch (bpp) {

	case 18:

		misc_val |= (0x0 << 5);

		break;

	case 30:

		misc_val |= (0x2 << 5);

		break;

	case 24:

	default:

		misc_val |= (0x1 << 5);

	}



	misc_val |= BIT(0); /* Configure clock to synchronous mode */



	pr_debug("Misc settings = 0x%x\n", misc_val);

	writel_relaxed(misc_val, ctrl_io->base + DP_MISC1_MISC0);

}



void mdss_dp_setup_tr_unit(struct dss_io_data *ctrl_io, u8 link_rate,
@@ -267,8 +305,6 @@ void mdss_dp_setup_tr_unit(struct dss_io_data *ctrl_io, u8 link_rate, 
	u32 valid_boundary2 = 0x0;

	struct dp_vc_tu_mapping_table const *tu_entry = tu_table;



	writel_relaxed(0x21, ctrl_io->base + DP_MISC1_MISC0);



	for (; tu_entry != tu_table + ARRAY_SIZE(tu_table); ++tu_entry) {

		if ((tu_entry->vic == res) &&

			(tu_entry->lanes == ln_cnt) &&