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Commit 855e0a4c authored by Sushmita Susheelendra's avatar Sushmita Susheelendra
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drm/msm: Set the TTBR1 range for a 36-bit address space 



Define a 36-bit address space for TTBR1 which is used for
kernel side GPU buffer objects.

Change-Id: I1c4eaee0fd92236793621c7d3dba1700e56fefd2
Signed-off-by: default avatarSushmita Susheelendra <ssusheel@codeaurora.org>
parent b39c6090

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+2 −2
Original line number Diff line number Diff line
@@ -1408,8 +1408,8 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) 
	 * Set the user domain range to fall into the TTBR1 region for global

	 * objects

	 */

	a5xx_config.va_start = 0x800000000;

	a5xx_config.va_end = 0x8ffffffff;

	a5xx_config.va_start = 0xfffffff000000000ULL;

	a5xx_config.va_end = 0xffffffffffffffffULL;



	a5xx_config.secure_va_start = SECURE_VA_START;

	a5xx_config.secure_va_end = SECURE_VA_START + SECURE_VA_SIZE - 1;