Commit 851b714b authored Sep 06, 2012 by Huang Shijie Committed by Greg Kroah-Hartman Sep 06, 2012

serial: mxs-auart: fix the wrong setting order



After set the AUART_CTRL0_CLKGATE, the UART will gate all the clocks off.
So the following line will not take effect.
       ................................................................
 	writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
 			u->membase + AUART_INTR_CLR);
       ................................................................

To fix this issue, the patch moves this gate-off line to
the end of setting registers.

Signed-off-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent 37cd0c99

drivers/tty/serial/mxs-auart.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -457,11 +457,11 @@ static void mxs_auart_shutdown(struct uart_port *u)

		writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);

		writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);

		writel(AUART_INTR_RXIEN \| AUART_INTR_RTIEN \| AUART_INTR_CTSMIEN,
		u->membase + AUART_INTR_CLR);

		writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);

		clk_disable_unprepare(s->clk);
		}