staging: fw-api: Merge CAF tag LA.UM.8.4.r1-05300-8x98.0 (8474405b) · Commits · e / devices / android_kernel_sony_msm8998

drivers/staging/fw-api/fw/htt.h

+250 −1

Original line number	Diff line number	Diff line
		@@ -198,9 +198,12 @@
		* 3.74 Add HTT_T2H_MSG_TYPE_RX_FISA_CFG msg.
		* 3.75 Add fp_ndp and mo_ndp flags in HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG.
		* 3.76 Add HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG msg.
		* 3.77 Add HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE msg.
		* 3.78 Add htt_ppdu_id def.
		* 3.79 Add HTT_NUM_AC_WMM def.
		*/
		#define HTT_CURRENT_VERSION_MAJOR 3
		#define HTT_CURRENT_VERSION_MINOR 76
		#define HTT_CURRENT_VERSION_MINOR 79

		#define HTT_NUM_TX_FRAG_DESC 1024

		@@ -250,6 +253,9 @@ enum HTT_AC_WMM {
		HTT_AC_WMM_BK = 0x1,
		HTT_AC_WMM_VI = 0x2,
		HTT_AC_WMM_VO = 0x3,

		HTT_NUM_AC_WMM = 0x4,

		/* extension Access Categories */
		HTT_AC_EXT_NON_QOS = 0x4,
		HTT_AC_EXT_UCAST_MGMT = 0x5,
		@@ -544,6 +550,7 @@ enum htt_h2t_msg_type {
		HTT_H2T_MSG_TYPE_CHAN_CALDATA = 0x14,
		HTT_H2T_MSG_TYPE_RX_FISA_CFG = 0x15,
		HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG = 0x16,
		HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17,

		/* keep this last */
		HTT_H2T_NUM_MSGS
		@@ -6512,6 +6519,135 @@ PREPACK struct htt_h2t_msg_rx_fse_operation_t {
		reserved:24;
		} POSTPACK;

		/**
		* @brief Host-->target HTT RX Full monitor mode register configuration message
		* @details
		* The host will send this Full monitor mode register configuration message.
		* This message can be sent per SOC or per PDEV which is differentiated
		* by pdev id values.
		*
		* \|31 16\|15 11\|10 8\|7 3\|2\|1\|0\|
		* \|-------------------------------------------------------------\|
		* \| reserved \| pdev_id \| MSG_TYPE \|
		* \|-------------------------------------------------------------\|
		* \| reserved \|Release Ring \|N\|Z\|E\|
		* \|-------------------------------------------------------------\|
		*
		* where E is 1-bit full monitor mode enable/disable.
		* Z is 1-bit additional descriptor for zero mpdu enable/disable
		* N is 1-bit additional descriptor for non zero mdpu enable/disable
		*
		* The following field definitions describe the format of the full monitor
		* mode configuration message sent from the host to target for each pdev.
		*
		* Header fields:
		* dword0 - b'7:0 - msg_type: This will be set to
		* HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE.
		* b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc
		* 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the
		* specified pdev's LMAC ring.
		* b'31:16 - reserved : Reserved for future use.
		* dword1 - b'0 - full_monitor_mode enable: This indicates that the full
		* monitor mode rxdma register is to be enabled or disabled.
		* b'1 - addnl_descs_zero_mpdus_end: This indicates that the
		* additional descriptors at ppdu end for zero mpdus
		* enabled or disabled.
		* b'2 - addnl_descs_non_zero_mpdus_end: This indicates that the
		* additional descriptors at ppdu end for non zero mpdus
		* enabled or disabled.
		* b'10:3 - release_ring: This indicates the destination ring
		* selection for the descriptor at the end of PPDU
		* 0 - REO ring select
		* 1 - FW ring select
		* 2 - SW ring select
		* 3 - Release ring select
		* Refer to htt_rx_full_mon_release_ring.
		* b'31:11 - reserved for future use
		*/
		PREPACK struct htt_h2t_msg_rx_full_monitor_mode_t {
		A_UINT32 msg_type:8,
		pdev_id:8,
		reserved0:16;
		A_UINT32 full_monitor_mode_enable:1,
		addnl_descs_zero_mpdus_end:1,
		addnl_descs_non_zero_mpdus_end:1,
		release_ring:8,
		reserved1:21;
		} POSTPACK;

		/**
		* Enumeration for full monitor mode destination ring select
		* 0 - REO destination ring select
		* 1 - FW destination ring select
		* 2 - SW destination ring select
		* 3 - Release destination ring select
		*/
		enum htt_rx_full_mon_release_ring {
		HTT_RX_MON_RING_REO,
		HTT_RX_MON_RING_FW,
		HTT_RX_MON_RING_SW,
		HTT_RX_MON_RING_RELEASE,
		};

		#define HTT_RX_FULL_MONITOR_MODE_SETUP_SZ (sizeof(struct htt_h2t_msg_rx_full_monitor_mode_t))
		/* DWORD 0: Pdev ID */
		#define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_M 0x0000ff00
		#define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S 8
		#define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_GET(_var) \
		(((_var) & HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_M) >> \
		HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S)
		#define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID, _val); \
		((_var) \|= ((_val) << HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S)); \
		} while (0)

		/* DWORD 1:ENABLE */
		#define HTT_RX_FULL_MONITOR_MODE_ENABLE_M 0x00000001
		#define HTT_RX_FULL_MONITOR_MODE_ENABLE_S 0

		#define HTT_RX_FULL_MONITOR_MODE_ENABLE_SET(word, enable) \
		do { \
		HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_ENABLE, enable); \
		(word) \|= ((enable) << HTT_RX_FULL_MONITOR_MODE_ENABLE_S); \
		} while (0)
		#define HTT_RX_FULL_MONITOR_MODE_ENABLE_GET(word) \
		(((word) & HTT_RX_FULL_MONITOR_MODE_ENABLE_M) >> HTT_RX_FULL_MONITOR_MODE_ENABLE_S)

		/* DWORD 1:ZERO_MPDU */
		#define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_M 0x00000002
		#define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S 1
		#define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_SET(word, zerompdu) \
		do { \
		HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU, zerompdu); \
		(word) \|= ((zerompdu) << HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S); \
		} while (0)
		#define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_GET(word) \
		(((word) & HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_M) >> HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S)


		/* DWORD 1:NON_ZERO_MPDU */
		#define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_M 0x00000004
		#define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S 2
		#define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_SET(word, nonzerompdu) \
		do { \
		HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU, nonzerompdu); \
		(word) \|= ((nonzerompdu) << HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S); \
		} while (0)
		#define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_GET(word) \
		(((word) & HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_M) >> HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S)

		/* DWORD 1:RELEASE_RINGS */
		#define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_M 0x000007f8
		#define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S 3
		#define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_SET(word, releaserings) \
		do { \
		HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS, releaserings); \
		(word) \|= ((releaserings) << HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S); \
		} while (0)
		#define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_GET(word) \
		(((word) & HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_M) >> HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S)

		/**
		* Enumeration for IP Protocol or IPSEC Protocol
		* IPsec describes the framework for providing security at IP layer.
		@@ -13870,4 +14006,117 @@ PREPACK struct htt_chan_caldata_msg {
		((_var) \|= ((_val) << HTT_CHAN_CALDATA_MSG_FREQ2_S)); \
		} while (0)


		/**
		* @brief - HTT PPDU ID format
		*
		* @details
		* The following field definitions describe the format of the PPDU ID.
		* The PPDU ID is truncated to 24 bits for TLVs from TQM.
		*
		* \|31 30\|29 24\| 23\| 22\|21 19\|18 17\|16 12\|11 0\|
		* +---------------------------------------------------------------------------
		* \|rsvd \|seq_cmd_type\|tqm_cmd\| rsvd \|seq_idx\|mac_id\| hwq_ id \| sch id \|
		* +---------------------------------------------------------------------------
		*
		* sch id :Schedule command id
		* Bits [11 : 0] : monotonically increasing counter to track the
		* PPDU posted to a specific transmit queue.
		*
		* hwq_id: Hardware Queue ID.
		* Bits [16 : 12] : Indicates the queue id in the hardware transmit queue.
		*
		* mac_id: MAC ID
		* Bits [18 : 17] : LMAC ID obtained from the whal_mac_struct
		*
		* seq_idx: Sequence index.
		* Bits [21 : 19] : Sequence index indicates all the PPDU belonging to
		* a particular TXOP.
		*
		* tqm_cmd: HWSCH/TQM flag.
		* Bit [23] : Always set to 0.
		*
		* seq_cmd_type: Sequence command type.
		* Bit [29 : 24] : Indicates the frame type for the current sequence.
		* Refer to enum HTT_STATS_FTYPE for values.
		*/
		PREPACK struct htt_ppdu_id {
		A_UINT32
		sch_id: 12,
		hwq_id: 5,
		mac_id: 2,
		seq_idx: 3,
		reserved1: 1,
		tqm_cmd: 1,
		seq_cmd_type: 6,
		reserved2: 2;
		} POSTPACK;

		#define HTT_PPDU_ID_SCH_ID_S 0
		#define HTT_PPDU_ID_SCH_ID_M 0x00000fff
		#define HTT_PPDU_ID_SCH_ID_GET(_var) \
		(((_var) & HTT_PPDU_ID_SCH_ID_M) >> HTT_PPDU_ID_SCH_ID_S)

		#define HTT_PPDU_ID_SCH_ID_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_PPDU_ID_SCH_ID, _val); \
		((_var) \|= ((_val) << HTT_PPDU_ID_SCH_ID_S)); \
		} while (0)

		#define HTT_PPDU_ID_HWQ_ID_S 12
		#define HTT_PPDU_ID_HWQ_ID_M 0x0001f000
		#define HTT_PPDU_ID_HWQ_ID_GET(_var) \
		(((_var) & HTT_PPDU_ID_HWQ_ID_M) >> HTT_PPDU_ID_HWQ_ID_S)

		#define HTT_PPDU_ID_HWQ_ID_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_PPDU_ID_HWQ_ID, _val); \
		((_var) \|= ((_val) << HTT_PPDU_ID_HWQ_ID_S)); \
		} while (0)

		#define HTT_PPDU_ID_MAC_ID_S 17
		#define HTT_PPDU_ID_MAC_ID_M 0x00060000
		#define HTT_PPDU_ID_MAC_ID_GET(_var) \
		(((_var) & HTT_PPDU_ID_MAC_ID_M) >> HTT_PPDU_ID_MAC_ID_S)

		#define HTT_PPDU_ID_MAC_ID_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_PPDU_ID_MAC_ID, _val); \
		((_var) \|= ((_val) << HTT_PPDU_ID_MAC_ID_S)); \
		} while (0)

		#define HTT_PPDU_ID_SEQ_IDX_S 19
		#define HTT_PPDU_ID_SEQ_IDX_M 0x00380000
		#define HTT_PPDU_ID_SEQ_IDX_GET(_var) \
		(((_var) & HTT_PPDU_ID_SEQ_IDX_M) >> HTT_PPDU_ID_SEQ_IDX_S)

		#define HTT_PPDU_ID_SEQ_IDX_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_PPDU_ID_SEQ_IDX, _val); \
		((_var) \|= ((_val) << HTT_PPDU_ID_SEQ_IDX_S)); \
		} while (0)

		#define HTT_PPDU_ID_TQM_CMD_S 23
		#define HTT_PPDU_ID_TQM_CMD_M 0x00800000
		#define HTT_PPDU_ID_TQM_CMD_GET(_var) \
		(((_var) & HTT_PPDU_ID_TQM_CMD_M) >> HTT_PPDU_ID_TQM_CMD_S)

		#define HTT_PPDU_ID_TQM_CMD_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_PPDU_ID_TQM_CMD, _val); \
		((_var) \|= ((_val) << HTT_PPDU_ID_TQM_CMD_S)); \
		} while (0)

		#define HTT_PPDU_ID_SEQ_CMD_TYPE_S 24
		#define HTT_PPDU_ID_SEQ_CMD_TYPE_M 0x3f000000
		#define HTT_PPDU_ID_SEQ_CMD_TYPE_GET(_var) \
		(((_var) & HTT_PPDU_ID_SEQ_CMD_TYPE_M) >> HTT_PPDU_ID_SEQ_CMD_TYPE_S)

		#define HTT_PPDU_ID_SEQ_CMD_TYPE_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_PPDU_ID_SEQ_CMD_TYPE, _val); \
		((_var) \|= ((_val) << HTT_PPDU_ID_SEQ_CMD_TYPE_S)); \
		} while (0)


		#endif

drivers/staging/fw-api/fw/htt_ppdu_stats.h

+116 −2

Original line number	Diff line number	Diff line
		@@ -46,6 +46,7 @@ enum htt_ppdu_stats_tlv_tag {
		HTT_PPDU_STATS_USR_COMMON_ARRAY_TLV, /* htt_ppdu_stats_usr_common_array_tlv_v */
		HTT_PPDU_STATS_INFO_TLV, /* htt_ppdu_stats_info */
		HTT_PPDU_STATS_TX_MGMTCTRL_PAYLOAD_TLV, /* htt_ppdu_stats_tx_mgmtctrl_payload_tlv */
		HTT_PPDU_STATS_USERS_INFO_TLV, /* htt_ppdu_stats_users_info_tlv */

		/* New TLV's are added above to this line */
		HTT_PPDU_STATS_MAX_TAG,
		@@ -535,6 +536,54 @@ typedef enum HTT_PPDU_STATS_SEQ_TYPE HTT_PPDU_STATS_SEQ_TYPE;
		((_var) \|= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BEAM_CHANGE_S)); \
		} while (0)

		#define HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION_M 0x02000000
		#define HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION_S 25

		#define HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION_GET(_var) \
		(((_var) & HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION_M) >> \
		HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION_S)

		#define HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION, _val); \
		((_var) \|= ((_val) << HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION_S)); \
		} while (0)

		enum HTT_PPDU_STATS_SPATIAL_REUSE {
		HTT_SRP_DISALLOW = 0,
		/* values 1-12 are reserved */
		HTT_SR_RESTRICTED = 13,
		HTT_SR_DELAY = 14,
		HTT_SRP_AND_NON_SRG_OBSS_PD_PROHIBITED = 15,
		};
		typedef enum HTT_PPDU_STATS_SPATIAL_REUSE HTT_PPDU_STATS_SPATIAL_REUSE;

		#define HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE_M 0x3c000000
		#define HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE_S 26

		#define HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE_GET(_var) \
		(((_var) & HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE_M) >> \
		HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE_S)

		#define HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE, _val); \
		((_var) \|= ((_val) << HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE_S)); \
		} while (0)

		#define HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_M 0x0000003f
		#define HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_S 0

		#define HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_GET(_var) \
		(((_var) & HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_M) >> \
		HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_S)

		#define HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID, _val); \
		((_var) \|= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_S)); \
		} while (0)

		typedef struct {
		htt_tlv_hdr_t tlv_hdr;

		@@ -634,25 +683,46 @@ typedef struct {
		* then beam_change = 0.
		* If we apply TxBF only starting from HE portion,
		* then beam_change = 1.
		* BIT [31 : 25] - reserved
		* BIT [25 : 25] - doppler_indication
		* BIT [29 : 26] - spatial_reuse for HE_SU,HE_MU and HE_EXT_SU format PPDU
		* HTT_PPDU_STATS_SPATIAL_REUSE
		* BIT [31 : 30] - reserved
		*/
		union {
		A_UINT32 reserved__ppdu_tx_time_us;
		A_UINT32 reserved__num_ul_expected_users__ppdu_tx_time_us;
		A_UINT32 reserved__spatial_reuse__doppler_indication__beam_change__num_ul_expected_users__ppdu_tx_time_us;
		struct {
		A_UINT32 phy_ppdu_tx_time_us: 16,
		num_ul_expected_users: 8,
		beam_change: 1,
		doppler_indication: 1,
		reserved1: 6;
		spatial_reuse: 4,
		reserved1: 2;
		};
		};

		/* ppdu_start_tstmp_u32_us:
		* Upper 32 bits of the PPDU start timestamp.
		* This field can be combined with the ppdu_start_tstmp_us field's
		* lower 32 bits of the PPDU start timestamp to form a 64-bit timestamp.
		*/
		A_UINT32 ppdu_start_tstmp_u32_us;

		/*
		* BIT [5 : 0] - bss_color_id indicates he_bss_color which is an identifier
		* of the BSS and is used to assist a receiving STA in
		* identifying the BSS from which a PPDU originates.
		* Value in the range 0 to 63
		* BIT [31 : 6] -reserved
		*/
		union {
		A_UINT32 reserved__bss_color_id;
		struct {
		A_UINT32 bss_color_id: 6,
		reserved2: 26;
		};
		};
		} htt_ppdu_stats_common_tlv;

		#define HTT_PPDU_STATS_USER_COMMON_TLV_TID_NUM_M 0x000000ff
		@@ -2189,5 +2259,49 @@ typedef struct {
		A_UINT32 payload[1];
		} htt_ppdu_stats_tx_mgmtctrl_payload_tlv;

		#define HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS_M 0x000000ff
		#define HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS_S 0

		#define HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS_GET(_var) \
		(((_var) & HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS_M) >> \
		HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS_S)

		#define HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS, _val); \
		((_var) \|= ((_val) << HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS_S)); \
		} while (0)

		#define HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE_M 0x0000ff00
		#define HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE_S 8

		#define HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE_GET(_var) \
		(((_var) & HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE_M) >> \
		HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE_S)

		#define HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE, _val); \
		((_var) \|= ((_val) << HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE_S)); \
		} while (0)

		typedef struct {
		htt_tlv_hdr_t tlv_hdr;

		/*
		* BIT [ 7 : 0] :- max_users
		* BIT [ 15 : 8] :- frame_type (HTT_STATS_FTYPE)
		* BIT [ 31 : 16] :- reserved1
		*/
		union {
		A_UINT32 rsvd__frame_type__max_users;
		struct {
		A_UINT32 max_users: 8,
		frame_type: 8,
		reserved1: 16;
		};
		};
		} htt_ppdu_stats_users_info_tlv;


		#endif //__HTT_PPDU_STATS_H__

drivers/staging/fw-api/fw/htt_stats.h

+314 −0

File changed.

Preview size limit exceeded, changes collapsed.

drivers/staging/fw-api/fw/wlan_defs.h

+82 −27

Original line number	Diff line number	Diff line
		@@ -290,33 +290,87 @@ typedef enum {
		#endif /* SUPPORT_11AX */

		enum {
		REGDMN_MODE_11A = 0x00000001, /* 11a channels */
		REGDMN_MODE_TURBO = 0x00000002, /* 11a turbo-only channels */
		REGDMN_MODE_11B = 0x00000004, /* 11b channels */
		REGDMN_MODE_PUREG = 0x00000008, /* 11g channels (OFDM only) */
		REGDMN_MODE_11G = 0x00000008, /* XXX historical */
		REGDMN_MODE_108G = 0x00000020, /* 11g+Turbo channels */
		REGDMN_MODE_108A = 0x00000040, /* 11a+Turbo channels */
		REGDMN_MODE_XR = 0x00000100, /* XR channels */
		REGDMN_MODE_11A_HALF_RATE = 0x00000200, /* 11A half rate channels */
		REGDMN_MODE_11A_QUARTER_RATE = 0x00000400, /* 11A quarter rate channels */
		REGDMN_MODE_11NG_HT20 = 0x00000800, /* 11N-G HT20 channels */
		REGDMN_MODE_11NA_HT20 = 0x00001000, /* 11N-A HT20 channels */
		REGDMN_MODE_11NG_HT40PLUS = 0x00002000, /* 11N-G HT40 + channels */
		REGDMN_MODE_11NG_HT40MINUS = 0x00004000, /* 11N-G HT40 - channels */
		REGDMN_MODE_11NA_HT40PLUS = 0x00008000, /* 11N-A HT40 + channels */
		REGDMN_MODE_11NA_HT40MINUS = 0x00010000, /* 11N-A HT40 - channels */
		REGDMN_MODE_11AC_VHT20 = 0x00020000, /* 5Ghz, VHT20 */
		REGDMN_MODE_11AC_VHT40PLUS = 0x00040000, /* 5Ghz, VHT40 + channels */
		REGDMN_MODE_11AC_VHT40MINUS = 0x00080000, /* 5Ghz VHT40 - channels */
		REGDMN_MODE_11AC_VHT80 = 0x000100000, /* 5Ghz, VHT80 channels */
		REGDMN_MODE_11AC_VHT20_2G = 0x000200000, /* 2Ghz, VHT20 */
		REGDMN_MODE_11AC_VHT40_2G = 0x000400000, /* 2Ghz, VHT40 */
		REGDMN_MODE_11AC_VHT80_2G = 0x000800000, /* 2Ghz, VHT80 */
		REGDMN_MODE_11AC_VHT160 = 0x001000000, /* 5Ghz, VHT160 */
		REGDMN_MODE_11AC_VHT40_2GPLUS = 0x002000000, /* 2Ghz, VHT40+ */
		REGDMN_MODE_11AC_VHT40_2GMINUS = 0x004000000, /* 2Ghz, VHT40- */
		REGDMN_MODE_11AC_VHT80_80 = 0x008000000, /* 5GHz, VHT80+80 */
		REGDMN_MODE_11A_BIT = 0, /* 11a channels */
		REGDMN_MODE_TURBO_BIT = 1, /* 11a turbo-only channels */
		REGDMN_MODE_11B_BIT = 2, /* 11b channels */
		REGDMN_MODE_PUREG_BIT = 3, /* 11g channels (OFDM only) */
		REGDMN_MODE_11G_BIT = 3, /* XXX historical */
		/* bit 4 is reserved */
		REGDMN_MODE_108G_BIT = 5, /* 11g+Turbo channels */
		REGDMN_MODE_108A_BIT = 6, /* 11a+Turbo channels */
		/* bit 7 is reserved */
		REGDMN_MODE_XR_BIT = 8, /* XR channels */
		REGDMN_MODE_11A_HALF_RATE_BIT = 9, /* 11A half rate channels */
		REGDMN_MODE_11A_QUARTER_RATE_BIT = 10, /* 11A quarter rate channels */
		REGDMN_MODE_11NG_HT20_BIT = 11, /* 11N-G HT20 channels */
		REGDMN_MODE_11NA_HT20_BIT = 12, /* 11N-A HT20 channels */
		REGDMN_MODE_11NG_HT40PLUS_BIT = 13, /* 11N-G HT40 + channels */
		REGDMN_MODE_11NG_HT40MINUS_BIT = 14, /* 11N-G HT40 - channels */
		REGDMN_MODE_11NA_HT40PLUS_BIT = 15, /* 11N-A HT40 + channels */
		REGDMN_MODE_11NA_HT40MINUS_BIT = 16, /* 11N-A HT40 - channels */
		REGDMN_MODE_11AC_VHT20_BIT = 17, /* 5Ghz, VHT20 */
		REGDMN_MODE_11AC_VHT40PLUS_BIT = 18, /* 5Ghz, VHT40 + channels */
		REGDMN_MODE_11AC_VHT40MINUS_BIT = 19, /* 5Ghz VHT40 - channels */
		REGDMN_MODE_11AC_VHT80_BIT = 20, /* 5Ghz, VHT80 channels */
		REGDMN_MODE_11AC_VHT20_2G_BIT = 21, /* 2Ghz, VHT20 */
		REGDMN_MODE_11AC_VHT40_2G_BIT = 22, /* 2Ghz, VHT40 */
		REGDMN_MODE_11AC_VHT80_2G_BIT = 23, /* 2Ghz, VHT80 */
		REGDMN_MODE_11AC_VHT160_BIT = 24, /* 5Ghz, VHT160 */
		REGDMN_MODE_11AC_VHT40_2GPLUS_BIT = 25, /* 2Ghz, VHT40+ */
		REGDMN_MODE_11AC_VHT40_2GMINUS_BIT = 26, /* 2Ghz, VHT40- */
		REGDMN_MODE_11AC_VHT80_80_BIT = 27, /* 5GHz, VHT80+80 */
		/* bits 28 to 31 are reserved */
		REGDMN_MODE_11AXG_HE20_BIT = 32, /* 2Ghz, HE20 */
		REGDMN_MODE_11AXA_HE20_BIT = 33, /* 5Ghz, HE20 */
		REGDMN_MODE_11AXG_HE40PLUS_BIT = 34, /* 2Ghz, HE40+ */
		REGDMN_MODE_11AXG_HE40MINUS_BIT = 35, /* 2Ghz, HE40- */
		REGDMN_MODE_11AXA_HE40PLUS_BIT = 36, /* 5Ghz, HE40+ */
		REGDMN_MODE_11AXA_HE40MINUS_BIT = 37, /* 5Ghz, HE40- */
		REGDMN_MODE_11AXA_HE80_BIT = 38, /* 5Ghz, HE80 */
		REGDMN_MODE_11AXA_HE160_BIT = 39, /* 5Ghz, HE160 */
		REGDMN_MODE_11AXA_HE80_80_BIT = 40, /* 5Ghz, HE80+80 */
		};

		enum {
		REGDMN_MODE_11A = 1 << REGDMN_MODE_11A_BIT, /* 11a channels */
		REGDMN_MODE_TURBO = 1 << REGDMN_MODE_TURBO_BIT, /* 11a turbo-only channels */
		REGDMN_MODE_11B = 1 << REGDMN_MODE_11B_BIT, /* 11b channels */
		REGDMN_MODE_PUREG = 1 << REGDMN_MODE_PUREG_BIT, /* 11g channels (OFDM only) */
		REGDMN_MODE_11G = 1 << REGDMN_MODE_11G_BIT, /* XXX historical */
		REGDMN_MODE_108G = 1 << REGDMN_MODE_108G_BIT, /* 11g+Turbo channels */
		REGDMN_MODE_108A = 1 << REGDMN_MODE_108A_BIT, /* 11a+Turbo channels */
		REGDMN_MODE_XR = 1 << REGDMN_MODE_XR_BIT, /* XR channels */
		REGDMN_MODE_11A_HALF_RATE = 1 << REGDMN_MODE_11A_HALF_RATE_BIT, /* 11A half rate channels */
		REGDMN_MODE_11A_QUARTER_RATE = 1 << REGDMN_MODE_11A_QUARTER_RATE_BIT, /* 11A quarter rate channels */
		REGDMN_MODE_11NG_HT20 = 1 << REGDMN_MODE_11NG_HT20_BIT, /* 11N-G HT20 channels */
		REGDMN_MODE_11NA_HT20 = 1 << REGDMN_MODE_11NA_HT20_BIT, /* 11N-A HT20 channels */
		REGDMN_MODE_11NG_HT40PLUS = 1 << REGDMN_MODE_11NG_HT40PLUS_BIT, /* 11N-G HT40 + channels */
		REGDMN_MODE_11NG_HT40MINUS = 1 << REGDMN_MODE_11NG_HT40MINUS_BIT, /* 11N-G HT40 - channels */
		REGDMN_MODE_11NA_HT40PLUS = 1 << REGDMN_MODE_11NA_HT40PLUS_BIT, /* 11N-A HT40 + channels */
		REGDMN_MODE_11NA_HT40MINUS = 1 << REGDMN_MODE_11NA_HT40MINUS_BIT, /* 11N-A HT40 - channels */
		REGDMN_MODE_11AC_VHT20 = 1 << REGDMN_MODE_11AC_VHT20_BIT, /* 5Ghz, VHT20 */
		REGDMN_MODE_11AC_VHT40PLUS = 1 << REGDMN_MODE_11AC_VHT40PLUS_BIT, /* 5Ghz, VHT40 + channels */
		REGDMN_MODE_11AC_VHT40MINUS = 1 << REGDMN_MODE_11AC_VHT40MINUS_BIT, /* 5Ghz VHT40 - channels */
		REGDMN_MODE_11AC_VHT80 = 1 << REGDMN_MODE_11AC_VHT80_BIT, /* 5Ghz, VHT80 channels */
		REGDMN_MODE_11AC_VHT20_2G = 1 << REGDMN_MODE_11AC_VHT20_2G_BIT, /* 2Ghz, VHT20 */
		REGDMN_MODE_11AC_VHT40_2G = 1 << REGDMN_MODE_11AC_VHT40_2G_BIT, /* 2Ghz, VHT40 */
		REGDMN_MODE_11AC_VHT80_2G = 1 << REGDMN_MODE_11AC_VHT80_2G_BIT, /* 2Ghz, VHT80 */
		REGDMN_MODE_11AC_VHT160 = 1 << REGDMN_MODE_11AC_VHT160_BIT, /* 5Ghz, VHT160 */
		REGDMN_MODE_11AC_VHT40_2GPLUS = 1 << REGDMN_MODE_11AC_VHT40_2GPLUS_BIT, /* 2Ghz, VHT40+ */
		REGDMN_MODE_11AC_VHT40_2GMINUS = 1 << REGDMN_MODE_11AC_VHT40_2GMINUS_BIT, /* 2Ghz, VHT40- */
		REGDMN_MODE_11AC_VHT80_80 = 1 << REGDMN_MODE_11AC_VHT80_80_BIT, /* 5GHz, VHT80+80 */
		};

		enum {
		REGDMN_MODE_U32_11AXG_HE20 = 1 << (REGDMN_MODE_11AXG_HE20_BIT - 32),
		REGDMN_MODE_U32_11AXA_HE20 = 1 << (REGDMN_MODE_11AXA_HE20_BIT - 32),
		REGDMN_MODE_U32_11AXG_HE40PLUS = 1 << (REGDMN_MODE_11AXG_HE40PLUS_BIT - 32),
		REGDMN_MODE_U32_11AXG_HE40MINUS = 1 << (REGDMN_MODE_11AXG_HE40MINUS_BIT - 32),
		REGDMN_MODE_U32_11AXA_HE40PLUS = 1 << (REGDMN_MODE_11AXA_HE40PLUS_BIT - 32),
		REGDMN_MODE_U32_11AXA_HE40MINUS = 1 << (REGDMN_MODE_11AXA_HE40MINUS_BIT - 32),
		REGDMN_MODE_U32_11AXA_HE80 = 1 << (REGDMN_MODE_11AXA_HE80_BIT - 32),
		REGDMN_MODE_U32_11AXA_HE160 = 1 << (REGDMN_MODE_11AXA_HE160_BIT - 32),
		REGDMN_MODE_U32_11AXA_HE80_80 = 1 << (REGDMN_MODE_11AXA_HE80_80_BIT - 32),
		};

		#define REGDMN_MODE_ALL (0xFFFFFFFF) /* REGDMN_MODE_ALL is defined out of the enum
		@@ -349,6 +403,7 @@ typedef struct {
		A_UINT32 high_2ghz_chan;
		A_UINT32 low_5ghz_chan;
		A_UINT32 high_5ghz_chan;
		A_UINT32 wireless_modes_ext; /* REGDMN MODE ext */
		} HAL_REG_CAPABILITIES;

		#ifdef NUM_SPATIAL_STREAM

drivers/staging/fw-api/fw/wmi_services.h

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