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Commit 8363983c authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add initial device tree files for msmtriton"

parents 981a0eae 63708968

Documentation/devicetree/bindings/arm/msm/msm.txt

+4 −0
Original line number Diff line number Diff line
@@ -92,6 +92,9 @@ SoCs: 
- MSMFALCON

  compatible = "qcom,msmfalcon"



- MSMTRITON

  compatible = "qcom,msmtriton"



- MSM8952

  compatible = "qcom,msm8952"
@@ -259,6 +262,7 @@ compatible = "qcom,msmhamster-cdp" 
compatible = "qcom,msmhamster-mtp"

compatible = "qcom,msmfalcon-sim"

compatible = "qcom,msmfalcon-rumi"

compatible = "qcom,msmtriton-rumi"

compatible = "qcom,msm8952-rumi"

compatible = "qcom,msm8952-sim"

compatible = "qcom,msm8952-qrd"

arch/arm/boot/dts/qcom/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -131,6 +131,8 @@ dtb-$(CONFIG_ARCH_MSMHAMSTER) += msmhamster-rumi.dtb 
dtb-$(CONFIG_ARCH_MSMFALCON) += msmfalcon-sim.dtb \

	msmfalcon-rumi.dtb



dtb-$(CONFIG_ARCH_MSMTRITON) += msmtriton-rumi.dtb



ifeq ($(CONFIG_ARM64),y)

always          := $(dtb-y)

subdir-y        := $(dts-dirs)

arch/arm/boot/dts/qcom/msmtriton-rumi.dts

0 → 100644
+29 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */





/dts-v1/;



#include "msmtriton.dtsi"

#include "msmfalcon-pinctrl.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. MSM TRITON RUMI";

	compatible = "qcom,msmtriton-rumi", "qcom,msmtriton", "qcom,rumi";

	qcom,board-id = <15 0>;

};



&uartblsp1dm1 {

	status = "ok";

	pinctrl-names = "default";

	pinctrl-0 = <&uart_console_active>;

};

arch/arm/boot/dts/qcom/msmtriton.dtsi

0 → 100644
+263 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include "skeleton64.dtsi"

#include <dt-bindings/clock/qcom,gcc-msmfalcon.h>

#include <dt-bindings/clock/qcom,gpu-msmfalcon.h>

#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	model = "Qualcomm Technologies, Inc. MSMTRITON";

	compatible = "qcom,msmtriton";

	qcom,msm-id = <318 0x0>;

	interrupt-parent = <&intc>;



	aliases {

		serial0 = &uartblsp1dm1;

	};



	chosen {

		stdout-path = "serial0";

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";

		};



		CPU1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x1>;

			enable-method = "psci";

		};



		CPU2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x2>;

			enable-method = "psci";

		};



		CPU3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x3>;

			enable-method = "psci";

		};



		CPU4: cpu@100 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

		};



		CPU5: cpu@101 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x101>;

			enable-method = "psci";

		};



		CPU6: cpu@102 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x102>;

			enable-method = "psci";

		};



		CPU7: cpu@103 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x103>;

			enable-method = "psci";

		};



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU4>;

				};



				core1 {

					cpu = <&CPU5>;

				};



				core2 {

					cpu = <&CPU6>;

				};



				core3 {

					cpu = <&CPU7>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&CPU0>;

				};



				core1 {

					cpu = <&CPU1>;

				};



				core2 {

					cpu = <&CPU2>;

				};



				core3 {

					cpu = <&CPU3>;

				};

			};

		};

	};



	soc: soc { };



};



&soc {

	#address-cells = <1>;

	#size-cells = <1>;

	ranges = <0 0 0 0xffffffff>;

	compatible = "simple-bus";



	intc: interrupt-controller@17a00000 {

		compatible = "arm,gic-v3";

		reg = <0x17a00000 0x10000>,       /* GICD */

		      <0x17b00000 0x100000>;      /* GICR * 8 */

		#interrupt-cells = <3>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		interrupt-controller;

		#redistributor-regions = <1>;

		redistributor-stride = <0x0 0x20000>;

		interrupts = <1 9 4>;

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <1 1 0xf08>,

			     <1 2 0xf08>,

			     <1 3 0xf08>,

			     <1 0 0xf08>;

		clock-frequency = <19200000>;

	};



	uartblsp1dm1: serial@0c170000 {

		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

		reg = <0xc170000 0x1000>;

		interrupts = <0 108 0>;

		status = "disabled";

		clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,

			 <&clock_gcc GCC_BLSP1_AHB_CLK>;

		clock-names = "core", "iface";

	};



	uartblsp2dm1: serial@0c1b0000 {

		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

		reg = <0xc1b0000 0x1000>;

		interrupts = <0 114 0>;

		status = "disabled";

		clocks = <&clock_gcc GCC_BLSP2_UART2_APPS_CLK>,

			 <&clock_gcc GCC_BLSP2_AHB_CLK>;

		clock-names = "core", "iface";

	};



	timer@17920000 {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		compatible = "arm,armv7-timer-mem";

		reg = <0x17920000 0x1000>;

		clock-frequency = <19200000>;



		frame@17921000 {

			frame-number = <0>;

			interrupts = <0 8 0x4>,

				     <0 7 0x4>;

			reg = <0x17921000 0x1000>,

			      <0x17922000 0x1000>;

		};



		frame@17923000 {

			frame-number = <1>;

			interrupts = <0 9 0x4>;

			reg = <0x17923000 0x1000>;

			status = "disabled";

		};



		frame@17924000 {

			frame-number = <2>;

			interrupts = <0 10 0x4>;

			reg = <0x17924000 0x1000>;

			status = "disabled";

		};



		frame@17925000 {

			frame-number = <3>;

			interrupts = <0 11 0x4>;

			reg = <0x17925000 0x1000>;

			status = "disabled";

		};



		frame@17926000 {

			frame-number = <4>;

			interrupts = <0 12 0x4>;

			reg = <0x17926000 0x1000>;

			status = "disabled";

		};



		frame@17927000 {

			frame-number = <5>;

			interrupts = <0 13 0x4>;

			reg = <0x17927000 0x1000>;

			status = "disabled";

		};



		frame@17928000 {

			frame-number = <6>;

			interrupts = <0 14 0x4>;

			reg = <0x17928000 0x1000>;

			status = "disabled";

		};

	};



	clock_gcc: qcom,dummycc {

		compatible = "qcom,dummycc";

		#clock-cells = <1>;

	};



	clock_mmss: qcom,dummycc {

		compatible = "qcom,dummycc";

		#clock-cells = <1>;

	};



	clock_gfx: qcom,dummycc {

		compatible = "qcom,dummycc";

		#clock-cells = <1>;

	};

};

arch/arm64/Kconfig.platforms

+9 −0
Original line number Diff line number Diff line
@@ -95,6 +95,15 @@ config ARCH_MSMFALCON 
	  If you do not wish to build a kernel that runs

	  on this chipset,say 'N' here.



config ARCH_MSMTRITON

	bool "Enable Support for Qualcomm Technologies Inc MSMTRITON"

	depends on ARCH_QCOM

	select COMMON_CLK_MSM

	help

	  This enables support for the MSMTRITON chipset.

	  If you do not wish to build a kernel that runs

	  on this chipset,say 'N' here.



config ARCH_ROCKCHIP

	bool "Rockchip Platforms"

	select ARCH_HAS_RESET_CONTROLLER