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Commit 82200b10 authored by Venkatesh Yadav Abbarapu's avatar Venkatesh Yadav Abbarapu
Browse files

ARM: dts: msm: Update debug uart support for msmfalcon 



As per the new schematic the debug uart is on BLSP1UART1
instead of BLSP2UART1.

Change-Id: I08b3ffa1a027b3212b77fe661348f2852485ed0d
Signed-off-by: default avatarVenkatesh Yadav Abbarapu <vabbar@codeaurora.org>
parent ab26d098

arch/arm/boot/dts/qcom/msmfalcon-rumi.dts

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 
	qcom,board-id = <15 0>;

};



&uartblsp2dm1 {

&uartblsp1dm1 {

	status = "ok";

	pinctrl-names = "default";

	pinctrl-0 = <&uart_console_active>;

arch/arm/boot/dts/qcom/msmfalcon-sim.dts

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 
	qcom,board-id = <16 0>;

};



&uartblsp2dm1 {

&uartblsp1dm1 {

	status = "ok";

	pinctrl-names = "default";

	pinctrl-0 = <&uart_console_active>;

arch/arm/boot/dts/qcom/msmfalcon.dtsi

+11 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 
	interrupt-parent = <&intc>;



	aliases {

		serial0 = &uartblsp2dm1;

		serial0 = &uartblsp1dm1;

	};



	chosen {
@@ -246,6 +246,16 @@ 
					3200 3200 3200 3200 3200 3200>;

	};



	uartblsp1dm1: serial@0c170000 {

		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

		reg = <0xc170000 0x1000>;

		interrupts = <0 108 0>;

		status = "disabled";

		clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,

			 <&clock_gcc GCC_BLSP1_AHB_CLK>;

		clock-names = "core", "iface";

	};



	uartblsp2dm1: serial@0c1b0000 {

		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

		reg = <0xc1b0000 0x1000>;