Loading Documentation/devicetree/bindings/drm/msm/mdp.txt +3 −0 Original line number Diff line number Diff line Loading @@ -3,6 +3,7 @@ Qualcomm Technologies,Inc. Adreno/Snapdragon display controller Required properties: Optional properties: - contiguous-region: reserved memory for HDMI and DSI buffer. - qcom,sde-plane-id-map: plane id mapping for virtual plane. - qcom,sde-plane-id: each virtual plane mapping node. - reg: reg property. Loading @@ -17,6 +18,8 @@ Optional properties: Example: &mdss_mdp { contiguous-region = <&cont_splash_mem &cont_splash_mem_hdmi>; qcom,sde-plane-id-map { qcom,sde-plane-id@0 { reg = <0x0>; Loading drivers/gpu/drm/msm/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -48,6 +48,7 @@ msm_drm-y := \ sde/sde_backlight.o \ sde/sde_color_processing.o \ sde/sde_vbif.o \ sde/sde_splash.o \ sde_dbg_evtlog.o \ sde_io_util.o \ dba_bridge.o \ Loading drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.c +26 −3 Original line number Diff line number Diff line Loading @@ -1253,6 +1253,13 @@ static int _sde_hdmi_hpd_enable(struct sde_hdmi *sde_hdmi) uint32_t hpd_ctrl; int i, ret; unsigned long flags; struct drm_connector *connector; struct msm_drm_private *priv; struct sde_kms *sde_kms; connector = hdmi->connector; priv = connector->dev->dev_private; sde_kms = to_sde_kms(priv->kms); for (i = 0; i < config->hpd_reg_cnt; i++) { ret = regulator_enable(hdmi->hpd_regs[i]); Loading Loading @@ -1292,9 +1299,11 @@ static int _sde_hdmi_hpd_enable(struct sde_hdmi *sde_hdmi) } } if (!sde_kms->splash_info.handoff) { sde_hdmi_set_mode(hdmi, false); _sde_hdmi_phy_reset(hdmi); sde_hdmi_set_mode(hdmi, true); } hdmi_write(hdmi, REG_HDMI_USEC_REFTIMER, 0x0001001b); Loading Loading @@ -2863,6 +2872,7 @@ int sde_hdmi_drm_init(struct sde_hdmi *display, struct drm_encoder *enc) struct msm_drm_private *priv = NULL; struct hdmi *hdmi; struct platform_device *pdev; struct sde_kms *sde_kms; DBG(""); if (!display || !display->drm_dev || !enc) { Loading Loading @@ -2921,6 +2931,19 @@ int sde_hdmi_drm_init(struct sde_hdmi *display, struct drm_encoder *enc) enc->bridge = hdmi->bridge; priv->bridges[priv->num_bridges++] = hdmi->bridge; /* * After initialising HDMI bridge, we need to check * whether the early display is enabled for HDMI. * If yes, we need to increase refcount of hdmi power * clocks. This can skip the clock disabling operation in * clock_late_init when finding clk.count == 1. */ sde_kms = to_sde_kms(priv->kms); if (sde_kms->splash_info.handoff) { sde_hdmi_bridge_power_on(hdmi->bridge); hdmi->power_on = true; } mutex_unlock(&display->display_lock); return 0; Loading drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.h +7 −0 Original line number Diff line number Diff line Loading @@ -357,6 +357,13 @@ int sde_hdmi_set_property(struct drm_connector *connector, int property_index, uint64_t value, void *display); /** * sde_hdmi_bridge_power_on -- A wrapper of _sde_hdmi_bridge_power_on. * @bridge: Handle to the drm bridge. * * Return: void. */ void sde_hdmi_bridge_power_on(struct drm_bridge *bridge); /** * sde_hdmi_get_property() - get the connector properties Loading drivers/gpu/drm/msm/hdmi-staging/sde_hdmi_bridge.c +5 −0 Original line number Diff line number Diff line Loading @@ -841,6 +841,11 @@ static bool _sde_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, return true; } void sde_hdmi_bridge_power_on(struct drm_bridge *bridge) { _sde_hdmi_bridge_power_on(bridge); } static const struct drm_bridge_funcs _sde_hdmi_bridge_funcs = { .pre_enable = _sde_hdmi_bridge_pre_enable, .enable = _sde_hdmi_bridge_enable, Loading Loading
Documentation/devicetree/bindings/drm/msm/mdp.txt +3 −0 Original line number Diff line number Diff line Loading @@ -3,6 +3,7 @@ Qualcomm Technologies,Inc. Adreno/Snapdragon display controller Required properties: Optional properties: - contiguous-region: reserved memory for HDMI and DSI buffer. - qcom,sde-plane-id-map: plane id mapping for virtual plane. - qcom,sde-plane-id: each virtual plane mapping node. - reg: reg property. Loading @@ -17,6 +18,8 @@ Optional properties: Example: &mdss_mdp { contiguous-region = <&cont_splash_mem &cont_splash_mem_hdmi>; qcom,sde-plane-id-map { qcom,sde-plane-id@0 { reg = <0x0>; Loading
drivers/gpu/drm/msm/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -48,6 +48,7 @@ msm_drm-y := \ sde/sde_backlight.o \ sde/sde_color_processing.o \ sde/sde_vbif.o \ sde/sde_splash.o \ sde_dbg_evtlog.o \ sde_io_util.o \ dba_bridge.o \ Loading
drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.c +26 −3 Original line number Diff line number Diff line Loading @@ -1253,6 +1253,13 @@ static int _sde_hdmi_hpd_enable(struct sde_hdmi *sde_hdmi) uint32_t hpd_ctrl; int i, ret; unsigned long flags; struct drm_connector *connector; struct msm_drm_private *priv; struct sde_kms *sde_kms; connector = hdmi->connector; priv = connector->dev->dev_private; sde_kms = to_sde_kms(priv->kms); for (i = 0; i < config->hpd_reg_cnt; i++) { ret = regulator_enable(hdmi->hpd_regs[i]); Loading Loading @@ -1292,9 +1299,11 @@ static int _sde_hdmi_hpd_enable(struct sde_hdmi *sde_hdmi) } } if (!sde_kms->splash_info.handoff) { sde_hdmi_set_mode(hdmi, false); _sde_hdmi_phy_reset(hdmi); sde_hdmi_set_mode(hdmi, true); } hdmi_write(hdmi, REG_HDMI_USEC_REFTIMER, 0x0001001b); Loading Loading @@ -2863,6 +2872,7 @@ int sde_hdmi_drm_init(struct sde_hdmi *display, struct drm_encoder *enc) struct msm_drm_private *priv = NULL; struct hdmi *hdmi; struct platform_device *pdev; struct sde_kms *sde_kms; DBG(""); if (!display || !display->drm_dev || !enc) { Loading Loading @@ -2921,6 +2931,19 @@ int sde_hdmi_drm_init(struct sde_hdmi *display, struct drm_encoder *enc) enc->bridge = hdmi->bridge; priv->bridges[priv->num_bridges++] = hdmi->bridge; /* * After initialising HDMI bridge, we need to check * whether the early display is enabled for HDMI. * If yes, we need to increase refcount of hdmi power * clocks. This can skip the clock disabling operation in * clock_late_init when finding clk.count == 1. */ sde_kms = to_sde_kms(priv->kms); if (sde_kms->splash_info.handoff) { sde_hdmi_bridge_power_on(hdmi->bridge); hdmi->power_on = true; } mutex_unlock(&display->display_lock); return 0; Loading
drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.h +7 −0 Original line number Diff line number Diff line Loading @@ -357,6 +357,13 @@ int sde_hdmi_set_property(struct drm_connector *connector, int property_index, uint64_t value, void *display); /** * sde_hdmi_bridge_power_on -- A wrapper of _sde_hdmi_bridge_power_on. * @bridge: Handle to the drm bridge. * * Return: void. */ void sde_hdmi_bridge_power_on(struct drm_bridge *bridge); /** * sde_hdmi_get_property() - get the connector properties Loading
drivers/gpu/drm/msm/hdmi-staging/sde_hdmi_bridge.c +5 −0 Original line number Diff line number Diff line Loading @@ -841,6 +841,11 @@ static bool _sde_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, return true; } void sde_hdmi_bridge_power_on(struct drm_bridge *bridge) { _sde_hdmi_bridge_power_on(bridge); } static const struct drm_bridge_funcs _sde_hdmi_bridge_funcs = { .pre_enable = _sde_hdmi_bridge_pre_enable, .enable = _sde_hdmi_bridge_enable, Loading