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Commit 7e41a98d authored by Jingchang Lu's avatar Jingchang Lu Committed by Shawn Guo
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dt-bindings: arm: add Freescale LS1021A SoC device tree binding

parent 034c4411
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+38 −0
Original line number Diff line number Diff line
@@ -74,3 +74,41 @@ Required root node properties:
i.MX6q generic board
Required root node properties:
    - compatible = "fsl,imx6q";


Freescale LS1021A Platform Device Tree Bindings
------------------------------------------------

Required root node compatible properties:
  - compatible = "fsl,ls1021a";

Freescale LS1021A SoC-specific Device Tree Bindings
-------------------------------------------

Freescale SCFG
  SCFG is the supplemental configuration unit, that provides SoC specific
configuration and status registers for the chip. Such as getting PEX port
status.
  Required properties:
  - compatible: should be "fsl,ls1021a-scfg"
  - reg: should contain base address and length of SCFG memory-mapped registers

Example:
	scfg: scfg@1570000 {
		compatible = "fsl,ls1021a-scfg";
		reg = <0x0 0x1570000 0x0 0x10000>;
	};

Freescale DCFG
  DCFG is the device configuration unit, that provides general purpose
configuration and status for the device. Such as setting the secondary
core start address and release the secondary core from holdoff and startup.
  Required properties:
  - compatible: should be "fsl,ls1021a-dcfg"
  - reg : should contain base address and length of DCFG memory-mapped registers

Example:
	dcfg: dcfg@1ee0000 {
		compatible = "fsl,ls1021a-dcfg";
		reg = <0x0 0x1ee0000 0x0 0x10000>;
	};