clk: qcom: Update the hmss_gpll0_clk_src to 300MHz

The GPLL0 source to the CPU subsystem requires 300MHz for OSM to use the
clock source. OSM internally cannot set the RCGR divider, so set the RCG to
300MHz at GCC.

Change-Id: I7a781c69656410eb4ce30126789dbaacf815e8ec
Signed-off-by: Taniya Das <tdas@codeaurora.org>