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Commit 7b2f8ee7 authored by Prasad Sodagudi's avatar Prasad Sodagudi
Browse files

arm64: Potential rollover condition for timer counter 



There is potential rollover condition for CNTVCT and
CNTPCT counters. So on any architecture timer counter
read, if the least significant 32 bits are set,
reread counter.

CRs-Fixed: 1074621
Change-Id: I136a5f0ee04deeb74c03800d591e44fbd9b4dd39
Signed-off-by: default avatarPrasad Sodagudi <psodagud@codeaurora.org>
parent cea5fb94

arch/arm64/include/asm/arch_timer.h

+7 −0
Original line number Diff line number Diff line
@@ -119,7 +119,14 @@ static inline u64 arch_counter_get_cntvct(void) 
	u64 cval;



	isb();

#if IS_ENABLED(CONFIG_MSM_TIMER_LEAP)

#define L32_BITS	0x00000000FFFFFFFF

	do {

		asm volatile("mrs %0, cntvct_el0" : "=r" (cval));

	} while ((cval & L32_BITS) == L32_BITS);

#else

	asm volatile("mrs %0, cntvct_el0" : "=r" (cval));

#endif



	return cval;

}

drivers/clocksource/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -158,6 +158,15 @@ config ARM_ARCH_TIMER_EVTSTREAM 
	  This must be disabled for hardware validation purposes to detect any

	  hardware anomalies of missing events.



config MSM_TIMER_LEAP

        bool "ARCH TIMER counter rollover"

        default n

        depends on ARM_ARCH_TIMER && ARM64

        help

          This option enables a check for least significant 32 bits of

          counter rollover. On every counter read if least significant

          32 bits are set, reread counter.



config ARM_GLOBAL_TIMER

	bool

	select CLKSRC_OF if OF