Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7b290616 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: msm: clock-local2: Remove checks for display RCG re-configuration"

parents e0b49f46 055e7860

drivers/clk/msm/clock-local2.c

+3 −34
Original line number Diff line number Diff line
@@ -1339,34 +1339,6 @@ static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */ 
	{0, 0},

};



static bool is_same_rcg_config(struct rcg_clk *rcg, struct clk_freq_tbl *freq,

			       bool has_mnd)

{

	u32 cfg;



	/* RCG update pending */

	if (readl_relaxed(CMD_RCGR_REG(rcg)) & CMD_RCGR_CONFIG_DIRTY_MASK)

		return false;

	if (has_mnd)

		if (readl_relaxed(M_REG(rcg)) != freq->m_val ||

		    readl_relaxed(N_REG(rcg)) != freq->n_val ||

		    readl_relaxed(D_REG(rcg)) != freq->d_val)

			return false;

	/*

	 * Both 0 and 1 represent same divider value in HW.

	 * Always use 0 to simplify comparison.

	 */

	if ((freq->div_src_val & CFG_RCGR_DIV_MASK) == 1)

		freq->div_src_val &= ~CFG_RCGR_DIV_MASK;

	cfg = readl_relaxed(CFG_RCGR_REG(rcg));

	if ((cfg & CFG_RCGR_DIV_MASK) == 1)

		cfg &= ~CFG_RCGR_DIV_MASK;

	if (cfg != freq->div_src_val)

		return false;



	return true;

}



static int set_rate_edp_pixel(struct clk *clk, unsigned long rate)

{

	struct rcg_clk *rcg = to_rcg_clk(clk);
@@ -1404,7 +1376,6 @@ static int set_rate_edp_pixel(struct clk *clk, unsigned long rate) 
			pixel_freq->d_val = ~frac->den;

		}

		spin_lock_irqsave(&local_clock_reg_lock, flags);

		if (!is_same_rcg_config(rcg, pixel_freq, true))

		__set_rate_mnd(rcg, pixel_freq);

		spin_unlock_irqrestore(&local_clock_reg_lock, flags);

		return 0;
@@ -1466,7 +1437,6 @@ static int set_rate_byte(struct clk *clk, unsigned long rate) 
	byte_freq->div_src_val |= BVAL(4, 0, div);



	spin_lock_irqsave(&local_clock_reg_lock, flags);

	if (!is_same_rcg_config(rcg, byte_freq, false))

	__set_rate_hid(rcg, byte_freq);

	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
@@ -1788,7 +1758,6 @@ static int rcg_clk_set_rate_dp(struct clk *clk, unsigned long rate) 
	}



	spin_lock_irqsave(&local_clock_reg_lock, flags);

	if (!is_same_rcg_config(rcg, freq_tbl, true))

	__set_rate_mnd(rcg, freq_tbl);

	spin_unlock_irqrestore(&local_clock_reg_lock, flags);

	return 0;