Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7a2469ce authored by Dhananjay Phadke's avatar Dhananjay Phadke Committed by David S. Miller
Browse files

netxen: cache msi register offset



Store msi target status register offset in adapter struct.
This avoids contention on msi_tgt_status table from interrupt
hadlers of different pci function.

Signed-off-by: default avatarDhananjay Phadke <dhananjay@netxen.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 61de71c6
Loading
Loading
Loading
Loading
+3 −0
Original line number Diff line number Diff line
@@ -1257,6 +1257,9 @@ struct netxen_adapter {
	u32 irq;
	u32 temp;

	u32 msi_tgt_status;
	u32 resv4;

	struct netxen_adapter_stats stats;

	struct netxen_recv_context recv_ctx;
+3 −1
Original line number Diff line number Diff line
@@ -525,6 +525,8 @@ netxen_setup_intr(struct netxen_adapter *adapter)
request_msi:
		if (use_msi && !pci_enable_msi(pdev)) {
			adapter->flags |= NETXEN_NIC_MSI_ENABLED;
			adapter->msi_tgt_status =
				msi_tgt_status[adapter->ahw.pci_func];
			dev_info(&pdev->dev, "using msi interrupts\n");
		} else
			dev_info(&pdev->dev, "using legacy interrupts\n");
@@ -1701,7 +1703,7 @@ static irqreturn_t netxen_msi_intr(int irq, void *data)

	/* clear interrupt */
	adapter->pci_write_immediate(adapter,
			msi_tgt_status[adapter->ahw.pci_func], 0xffffffff);
			adapter->msi_tgt_status, 0xffffffff);

	napi_schedule(&sds_ring->napi);
	return IRQ_HANDLED;