Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 75a35af1 authored by Linux Build Service Account's avatar Linux Build Service Account
Browse files

Promotion of kernel.lnx.4.4-161026. 

CRs      Change ID                                   Subject
--------------------------------------------------------------------------------------------------------------
1075375 1081701   Ie389e28ff890a805854f921e4cd491a296a32925   soc: qcom: Use a deferrable timer base for the msm watch
1081673   Ib75655d52e5d85d649ebfcb971caf3f5b0b6dc80   ASoC: wcd934x: Update CPR register defaults
1079363   I45847f446c91c80a5110d80b59a0ae4b8e2c40e5   smb-lib: update displaying battery overvoltage in health
1059495   Ibad70b1bb364b60439c4988e318105a733396db8   drivers: soc: Initialize return var to default value
1080799   I0c496a73feb83c640f9a135f98ec393d1096b205   USB: pd: Fix compilation issues for 32 bit support
1081725   I09b4bc37617811fd4acd86a7e4f5ef91630675df   coresight: tmc: skip tmc read if mem allocaiton failed
1022917   Ia02a1ffed911498dd6eb5df246e6da68a7802a92   ASoC: msmcobalt: Add independent clock support on codec
1081778   I9eebb4fb35aca2c8424bfb29ae9d833650dc5ad4   sched: Set curr/prev_window_cpu pointers to NULL in sche
1022917   Id5eee88e87e1e5d68ce34f43b4c85c6b48886b82   ARM: msm: dts: add second CPE session for msmcobalt
1081673   I92d0511b4e9912dfa346378784d811f6606df205   drivers: mfd: Mark CPR bank registers as volatile
1034169   I2e2b50aeb770ca523cf70e2c0768e38ee56e39eb   ASoC: wcd9335: Fix register sequence for CPE configurati
1073238   Ia537e776d0b322d56cd6003f95cdded5e695ceeb   soc: qcom: use interruptible wait_for_completion API
1080385   I346085ec722f491f96181ef1beb383710b441f4b   qpnp-fg-gen3: Fix storing nominal capacity to actual cap
1022917   I280057b17188757f586562f45f32ecf28595e045   ASoC: msmcobalt: Add CPE ECPP DAI instance for ECPP path
1081084   I44487bfcb4e21d76948cd836ad2dae18bc3d22f4   ARM: dts: msm: enable VDD_GFX CPR aging adjustments for
1081146   I63e8863efb91af891dbcbfc070dfdcd833ea3ad4   qpnp-fg-gen3: fix the error in showing battery temperatu

Change-Id: Ic0497abd3afc11946b2cc861a7a477836b713ad4
CRs-Fixed: 1081673, 1081146, 1073238, 1081778, 1080385, 1081725, 1059495, 1022917, 1075375, 1080799, 1034169, 1079363, 1081084, 1081701
parents 9ba9df83 e76e6c8d

arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi

+9 −2
Original line number Diff line number Diff line
@@ -85,14 +85,15 @@ 
		asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,

				<&loopback>, <&compress>, <&hostless>,

				<&afe>, <&lsm>, <&routing>, <&cpe>, <&compr>,

				<&pcm_noirq>;

				<&pcm_noirq>, <&cpe3>;

		asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",

				"msm-pcm-dsp.2", "msm-voip-dsp",

				"msm-pcm-voice", "msm-pcm-loopback",

				"msm-compress-dsp", "msm-pcm-hostless",

				"msm-pcm-afe", "msm-lsm-client",

				"msm-pcm-routing", "msm-cpe-lsm",

				"msm-compr-dsp", "msm-pcm-dsp-noirq";

				"msm-compr-dsp", "msm-pcm-dsp-noirq",

				"msm-cpe-lsm.3";

		asoc-cpu = <&dai_hdmi>, <&dai_dp>,

				<&dai_mi2s0>, <&dai_mi2s1>,

				<&dai_mi2s2>, <&dai_mi2s3>,
@@ -244,6 +245,12 @@ 


	cpe: qcom,msm-cpe-lsm {

		compatible = "qcom,msm-cpe-lsm";

		qcom,msm-cpe-lsm-id = <1>;

	};



	cpe3: qcom,msm-cpe-lsm@3 {

		compatible = "qcom,msm-cpe-lsm";

		qcom,msm-cpe-lsm-id = <3>;

	};



	qcom,wcd-dsp-mgr {

arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi

+25 −3
Original line number Diff line number Diff line
@@ -556,6 +556,7 @@ 


&gfx_cpr {

	compatible = "qcom,cpr4-msmcobalt-v2-mmss-regulator";

	qcom,cpr-aging-ref-voltage = <1024000>;

};



&gfx_vreg {
@@ -624,11 +625,32 @@ 
		    0    0 3487    0 3280 1896 1874    0>;



	qcom,cpr-open-loop-voltage-fuse-adjustment =

		<  100000        0        0        0>;

		<  100000        0        0        0>,

		<  100000        0        0        0>,

		<   85000  (-15000) (-15000) (-15000)>,

		<   85000  (-15000) (-15000) (-15000)>,

		<   85000  (-15000) (-15000) (-15000)>,

		<   85000  (-15000) (-15000) (-15000)>,

		<   85000  (-15000) (-15000) (-15000)>,

		<   85000  (-15000) (-15000) (-15000)>;



	qcom,cpr-closed-loop-voltage-adjustment =

		<   96000    18000     4000        0

			0    13000     9000        0>;

			0    13000     9000        0>,

		<   96000    18000     4000        0

			0    13000     9000        0>,

		<   81000     3000  (-11000) (-15000)

		  (-15000)  (-2000)  (-6000) (-15000)>,

		<   81000     3000  (-11000) (-15000)

		  (-15000)  (-2000)  (-6000) (-15000)>,

		<   81000     3000  (-11000) (-15000)

		  (-15000)  (-2000)  (-6000) (-15000)>,

		<   81000     3000  (-11000) (-15000)

		  (-15000)  (-2000)  (-6000) (-15000)>,

		<   81000     3000  (-11000) (-15000)

		  (-15000)  (-2000)  (-6000) (-15000)>,

		<   81000     3000  (-11000) (-15000)

		  (-15000)  (-2000)  (-6000) (-15000)>;



	qcom,cpr-floor-to-ceiling-max-range =

	       <50000 50000 50000 50000 50000 50000 70000 70000>;
@@ -642,7 +664,7 @@ 
	qcom,cpr-aging-max-voltage-adjustment = <15000>;

	qcom,cpr-aging-ref-corner = <8>;

	qcom,cpr-aging-ro-scaling-factor = <2950>;

	qcom,allow-aging-voltage-adjustment = <0>;

	qcom,allow-aging-voltage-adjustment = <0 0 1 1 1 1 1 1>;

};



&qusb_phy0 {

drivers/hwtracing/coresight/coresight-tmc.c

+6 −0
Original line number Diff line number Diff line
@@ -1143,6 +1143,12 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdata) 
		goto err;

	}



	if (drvdata->config_type == TMC_CONFIG_TYPE_ETR &&

	    drvdata->vaddr == NULL) {

		ret = -ENOMEM;

		goto err;

	}



	if (!drvdata->enable)

		goto out;

drivers/mfd/wcd934x-regmap.c

+3 −0
Original line number Diff line number Diff line
@@ -1904,6 +1904,9 @@ static bool wcd934x_is_volatile_register(struct device *dev, unsigned int reg) 
	    (reg <= WCD934X_CDC_ANC1_FB_GAIN_CTL))

		return true;



	if ((reg >= WCD934X_CODEC_CPR_WR_DATA_0) &&

	    (reg <= WCD934X_CODEC_CPR_RD_DATA_3))

		return true;



	/*

	 * Need to mark volatile for registers that are writable but

drivers/power/qcom-charger/qpnp-fg-gen3.c

+4 −4
Original line number Diff line number Diff line
@@ -506,8 +506,7 @@ static int fg_get_cc_soc_sw(struct fg_chip *chip, int *val) 
#define BATT_TEMP_DENR		1

static int fg_get_battery_temp(struct fg_chip *chip, int *val)

{

	int rc = 0;

	u16 temp = 0;

	int rc = 0, temp;

	u8 buf[2];



	rc = fg_read(chip, BATT_INFO_BATT_TEMP_LSB(chip), buf, 2);
@@ -925,10 +924,11 @@ static int fg_load_learned_cap_from_sram(struct fg_chip *chip) 
	}



	chip->cl.learned_cc_uah = act_cap_mah * 1000;



	if (chip->cl.learned_cc_uah != chip->cl.nom_cap_uah) {

		if (chip->cl.learned_cc_uah == 0)

			chip->cl.learned_cc_uah = chip->cl.nom_cap_uah;



	if (chip->cl.learned_cc_uah != chip->cl.nom_cap_uah) {

		delta_cc_uah = abs(chip->cl.learned_cc_uah -

					chip->cl.nom_cap_uah);

		pct_nom_cap_uah = div64_s64((int64_t)chip->cl.nom_cap_uah *