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Commit 74f63af0 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: mdss: enable pll regulator during phy on sequence"

parents 719eabd0 1a71e5ed

drivers/video/fbdev/msm/mdss_hdmi_tx.c

+7 −2
Original line number Diff line number Diff line
@@ -1773,7 +1773,7 @@ static int hdmi_tx_read_edid(struct hdmi_tx_ctrl *hdmi_ctrl) 
			check_sum += ebuf[ndx];



		if (check_sum & 0xFF) {

			DEV_ERR("%s: checksome mismatch\n", __func__);

			DEV_ERR("%s: checksum mismatch\n", __func__);

			ret = -EINVAL;

			goto end;

		}
@@ -2328,6 +2328,8 @@ static void hdmi_tx_update_deep_color(struct hdmi_tx_ctrl *hdmi_ctrl) 
static void hdmi_tx_hpd_int_work(struct work_struct *work)

{

	struct hdmi_tx_ctrl *hdmi_ctrl = NULL;

	int rc = -EINVAL;

	int retry = MAX_EDID_READ_RETRY;



	hdmi_ctrl = container_of(work, struct hdmi_tx_ctrl, hpd_int_work);

	if (!hdmi_ctrl) {
@@ -2346,7 +2348,10 @@ static void hdmi_tx_hpd_int_work(struct work_struct *work) 
		hdmi_ctrl->hpd_state ? "CONNECT" : "DISCONNECT");



	if (hdmi_ctrl->hpd_state) {

		hdmi_tx_read_sink_info(hdmi_ctrl);

		while (rc && retry--)

			rc = hdmi_tx_read_sink_info(hdmi_ctrl);

		if (!retry && rc)

			pr_warn_ratelimited("%s: EDID read failed\n", __func__);

		hdmi_tx_update_deep_color(hdmi_ctrl);



		hdmi_tx_send_cable_notification(hdmi_ctrl, true);

drivers/video/fbdev/msm/msm_mdss_io_8974.c

+10 −1
Original line number Diff line number Diff line
@@ -947,8 +947,11 @@ static void mdss_dsi_8996_phy_power_off( 
{

	int ln;

	void __iomem *base;

	u32 data;



	MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0x7f);

	/* Turn off PLL power */

	data = MIPI_INP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0);

	MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, data & ~BIT(7));



	/* 4 lanes + clk lane configuration */

	for (ln = 0; ln < 5; ln++) {
@@ -1004,6 +1007,7 @@ static void mdss_dsi_8996_phy_power_on( 
	void __iomem *base;

	struct mdss_dsi_phy_ctrl *pd;

	char *ip;

	u32 data;



	pd = &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db);
@@ -1023,6 +1027,10 @@ static void mdss_dsi_8996_phy_power_on( 
	}



	mdss_dsi_8996_phy_regulator_enable(ctrl);



	/* Turn on PLL power */

	data = MIPI_INP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0);

	MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, data | BIT(7));

}



static void mdss_dsi_phy_power_on(
@@ -1126,6 +1134,7 @@ static void mdss_dsi_8996_phy_config(struct mdss_dsi_ctrl_pdata *ctrl) 
			mdss_dsi_8996_pll_source_standalone(ctrl);

	}



	MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0x7f);

	wmb(); /* make sure registers committed */

}