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Commit 7438a89b authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "Merge android-4.4@64a73ff (v4.4.76) into msm-4.4"

parents d03efe4d 4c8daae4

Makefile

+7 −7
Original line number Diff line number Diff line 
VERSION = 4

PATCHLEVEL = 4

SUBLEVEL = 75

SUBLEVEL = 76

EXTRAVERSION =

NAME = Blurry Fish Butt
@@ -637,6 +637,12 @@ endif 
# Tell gcc to never replace conditional load with a non-conditional one

KBUILD_CFLAGS	+= $(call cc-option,--param=allow-store-data-races=0)



# check for 'asm goto'

ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-goto.sh $(CC) $(KBUILD_CFLAGS)), y)

	KBUILD_CFLAGS += -DCC_HAVE_ASM_GOTO

	KBUILD_AFLAGS += -DCC_HAVE_ASM_GOTO

endif



ifdef CONFIG_READABLE_ASM

# Disable optimizations that make assembler listings hard to read.

# reorder blocks reorders the control in the function
@@ -792,12 +798,6 @@ KBUILD_CFLAGS += $(call cc-option,-Werror=date-time) 
# use the deterministic mode of AR if available

KBUILD_ARFLAGS := $(call ar-option,D)



# check for 'asm goto'

ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-goto.sh $(CC) $(KBUILD_CFLAGS)), y)

	KBUILD_CFLAGS += -DCC_HAVE_ASM_GOTO

	KBUILD_AFLAGS += -DCC_HAVE_ASM_GOTO

endif



include scripts/Makefile.kasan

include scripts/Makefile.extrawarn

include scripts/Makefile.ubsan

arch/arm/boot/dts/bcm5301x.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -54,14 +54,14 @@ 
		timer@0200 {

			compatible = "arm,cortex-a9-global-timer";

			reg = <0x0200 0x100>;

			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;

			clocks = <&clk_periph>;

		};



		local-timer@0600 {

			compatible = "arm,cortex-a9-twd-timer";

			reg = <0x0600 0x100>;

			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;

			clocks = <&clk_periph>;

		};

arch/arm/mm/mmu.c

+4 −4
Original line number Diff line number Diff line
@@ -1197,15 +1197,15 @@ void __init sanity_check_meminfo(void) 


	high_memory = __va(arm_lowmem_limit - 1) + 1;



	if (!memblock_limit)

		memblock_limit = arm_lowmem_limit;



	/*

	 * Round the memblock limit down to a pmd size.  This

	 * helps to ensure that we will allocate memory from the

	 * last full pmd, which should be mapped.

	 */

	if (memblock_limit)

	memblock_limit = round_down(memblock_limit, PMD_SIZE);

	if (!memblock_limit)

		memblock_limit = arm_lowmem_limit;



	memblock_set_current_limit(memblock_limit);

}

arch/arm64/include/asm/acpi.h

+3 −3
Original line number Diff line number Diff line
@@ -23,8 +23,8 @@ 
	(acpi_gbl_FADT.header.revision < 6 ? 76 : 80)



#define BAD_MADT_GICC_ENTRY(entry, end)					\

	(!(entry) || (unsigned long)(entry) + sizeof(*(entry)) > (end) ||	\

	 (entry)->header.length != ACPI_MADT_GICC_LENGTH)

	(!(entry) || (entry)->header.length != ACPI_MADT_GICC_LENGTH ||	\

	(unsigned long)(entry) + ACPI_MADT_GICC_LENGTH > (end))



/* Basic configuration for ACPI */

#ifdef	CONFIG_ACPI

arch/mips/ath79/common.c

+8 −8
Original line number Diff line number Diff line
@@ -76,14 +76,14 @@ void ath79_ddr_set_pci_windows(void) 
{

	BUG_ON(!ath79_ddr_pci_win_base);



	__raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0);

	__raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 1);

	__raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 2);

	__raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 3);

	__raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 4);

	__raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 5);

	__raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 6);

	__raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 7);

	__raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0);

	__raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4);

	__raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8);

	__raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc);

	__raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10);

	__raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14);

	__raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18);

	__raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c);

}

EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows);