Loading arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -75,6 +75,8 @@ coresight-name = "coresight-tmc-etf"; arm,default-sink; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "apb_pclk", "core_a_clk"; Loading Loading
arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -75,6 +75,8 @@ coresight-name = "coresight-tmc-etf"; arm,default-sink; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "apb_pclk", "core_a_clk"; Loading