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Commit 734e0fe2 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: pcie: add support for switch latency"

parents e29d253e 12fe1aaf

Documentation/devicetree/bindings/pci/msm_pcie.txt

+4 −0
Original line number Diff line number Diff line
@@ -97,6 +97,9 @@ Optional Properties: 
    and assign for each endpoint.

  - qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become

    stable after power on, before de-assert the PERST to the endpoint.

  - qcom,switch-latency: The time (unit: ms) to wait for the PCIe endpoint's link

    training with switch downstream port after the link between switch upstream

    port and RC is up.

  - qcom,wr-halt-size: With base 2, this exponent determines the size of the

    data that PCIe core will halt on for each write transaction.

  - qcom,cpl-timeout: Completion timeout value. This value specifies the time range
@@ -276,6 +279,7 @@ Example: 
		qcom,smmu-exist;

		qcom,smmu-sid-base = <0x1480>;

		qcom,ep-latency = <100>;

		qcom,switch-latency = <100>;

		qcom,wr-halt-size = <0xa>; /* 1KB */

		qcom,cpl-timeout = <0x2>;

drivers/pci/host/pci-msm.c

+27 −1
Original line number Diff line number Diff line
@@ -278,6 +278,7 @@ 


#define PERST_PROPAGATION_DELAY_US_MIN	  1000

#define PERST_PROPAGATION_DELAY_US_MAX	  1005

#define SWITCH_DELAY_MAX	  20

#define REFCLK_STABILIZATION_DELAY_US_MIN     1000

#define REFCLK_STABILIZATION_DELAY_US_MAX     1005

#define LINK_UP_TIMEOUT_US_MIN		    5000
@@ -626,6 +627,7 @@ struct msm_pcie_dev_t { 
	bool				 ext_ref_clk;

	bool				common_phy;

	uint32_t			   ep_latency;

	uint32_t			switch_latency;

	uint32_t			wr_halt_size;

	uint32_t			cpl_timeout;

	uint32_t			current_bdf;
@@ -1984,6 +1986,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) 
		dev->common_phy);

	PCIE_DBG_FS(dev, "ep_latency: %dms\n",

		dev->ep_latency);

	PCIE_DBG_FS(dev, "switch_latency: %dms\n",

		dev->switch_latency);

	PCIE_DBG_FS(dev, "wr_halt_size: 0x%x\n",

		dev->wr_halt_size);

	PCIE_DBG_FS(dev, "cpl_timeout: 0x%x\n",
@@ -4675,7 +4679,15 @@ int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) 
		goto link_fail;

	}



	msleep(500);

	if (dev->switch_latency) {

		PCIE_DBG(dev, "switch_latency: %dms\n",

			dev->switch_latency);

		if (dev->switch_latency <= SWITCH_DELAY_MAX)

			usleep_range(dev->switch_latency * 1000,

				dev->switch_latency * 1000);

		else

			msleep(dev->switch_latency);

	}



	msm_pcie_config_controller(dev);
@@ -6279,6 +6291,20 @@ static int msm_pcie_probe(struct platform_device *pdev) 
		PCIE_DBG(&msm_pcie_dev[rc_idx], "RC%d: ep-latency: 0x%x.\n",

			rc_idx, msm_pcie_dev[rc_idx].ep_latency);



	msm_pcie_dev[rc_idx].switch_latency = 0;

	ret = of_property_read_u32((&pdev->dev)->of_node,

					"qcom,switch-latency",

					&msm_pcie_dev[rc_idx].switch_latency);



	if (ret)

		PCIE_DBG(&msm_pcie_dev[rc_idx],

				"RC%d: switch-latency does not exist.\n",

				rc_idx);

	else

		PCIE_DBG(&msm_pcie_dev[rc_idx],

				"RC%d: switch-latency: 0x%x.\n",

				rc_idx, msm_pcie_dev[rc_idx].switch_latency);



	msm_pcie_dev[rc_idx].wr_halt_size = 0;

	ret = of_property_read_u32(pdev->dev.of_node,

				"qcom,wr-halt-size",