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Commit 71a6fa17 authored by Wang Dongsheng's avatar Wang Dongsheng Committed by Scott Wood
Browse files

powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define 



E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec
idle patches.

Signed-off-by: default avatarWang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent 1e83bf87

arch/powerpc/include/asm/reg.h

+2 −0
Original line number Diff line number Diff line
@@ -1075,6 +1075,8 @@ 
#define PVR_8560	0x80200000

#define PVR_VER_E500V1	0x8020

#define PVR_VER_E500V2	0x8021

#define PVR_VER_E6500	0x8040



/*

 * For the 8xx processors, all of them report the same PVR family for

 * the PowerPC core. The various versions of these processors must be

arch/powerpc/include/asm/reg_booke.h

+9 −0
Original line number Diff line number Diff line
@@ -171,6 +171,7 @@ 
#define SPRN_L2CSR1	0x3FA	/* L2 Data Cache Control and Status Register 1 */

#define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */

#define SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */

#define SPRN_PWRMGTCR0	0x3FB	/* Power management control register 0 */

#define SPRN_SVR	0x3FF	/* System Version Register */



/*
@@ -217,6 +218,14 @@ 
#define	CCR1_DPC	0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */

#define	CCR1_TCS	0x00000080 /* Timer Clock Select */



/* Bit definitions for PWRMGTCR0. */

#define PWRMGTCR0_PW20_WAIT		(1 << 14) /* PW20 state enable bit */

#define PWRMGTCR0_PW20_ENT_SHIFT	8

#define PWRMGTCR0_PW20_ENT		0x3F00

#define PWRMGTCR0_AV_IDLE_PD_EN		(1 << 22) /* Altivec idle enable */

#define PWRMGTCR0_AV_IDLE_CNT_SHIFT	16

#define PWRMGTCR0_AV_IDLE_CNT		0x3F0000



/* Bit definitions for the MCSR. */

#define MCSR_MCS	0x80000000 /* Machine Check Summary */

#define MCSR_IB		0x40000000 /* Instruction PLB Error */