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Commit 7043ad4f authored by Ralf Baechle's avatar Ralf Baechle Committed by
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MIPS: R2: Try to bulletproof instruction_hazard against miss-compilation. 


    
Gcc has a tradition of misscompiling the previous construct using the
address of a label as argument to inline assembler.  Gas otoh has the
annoying difference between la and dla which are only usable for 32-bit
rsp. 64-bit code, so can't be used without conditional compilation.
The alterantive is switching the assembler to 64-bit code which happens
to work right even for 32-bit code ...
    
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 15265251

include/asm-mips/hazards.h

+15 −5
Original line number Original line Diff line number Diff line
@@ -233,15 +233,25 @@ __asm__( 
#endif

#endif





#ifdef CONFIG_CPU_MIPSR2

#ifdef CONFIG_CPU_MIPSR2

/*

 * gcc has a tradition of misscompiling the previous construct using the

 * address of a label as argument to inline assembler.  Gas otoh has the

 * annoying difference between la and dla which are only usable for 32-bit

 * rsp. 64-bit code, so can't be used without conditional compilation.

 * The alterantive is switching the assembler to 64-bit code which happens

 * to work right even for 32-bit code ...

 */

#define instruction_hazard()						\

#define instruction_hazard()						\

do {									\

do {									\

__label__ __next;							\

	unsigned long tmp;						\

									\

	__asm__ __volatile__(						\

	__asm__ __volatile__(						\

	"	.set	mips64r2				\n"	\

	"	dla	%0, 1f					\n"	\

	"	jr.hb	%0					\n"	\

	"	jr.hb	%0					\n"	\

	:								\

	"	.set	mips0					\n"	\

	: "r" (&&__next));						\

	"1:							\n"	\

__next:									\

	: "=r" (tmp));							\

	;								\

} while (0)

} while (0)





#else

#else