Merge "clk: qcom: Add support for the turing vote clocks" (6f38194d) · Commits · e / devices / android_kernel_sony_msm8998

drivers/clk/qcom/gcc-msmfalcon.c

+30 −0

Original line number	Diff line number	Diff line
		@@ -2527,6 +2527,32 @@ static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = {
		},
		};

		static struct clk_branch hlos1_vote_turing_adsp_smmu_clk = {
		.halt_reg = 0x7d048,
		.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE,
		.clkr = {
		.enable_reg = 0x7d048,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "hlos1_vote_turing_adsp_smmu_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch hlos2_vote_turing_adsp_smmu_clk = {
		.halt_reg = 0x7e048,
		.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE,
		.clkr = {
		.enable_reg = 0x7e048,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "hlos2_vote_turing_adsp_smmu_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_fixed_factor gcc_ce1_ahb_m_clk = {
		.hw.init = &(struct clk_init_data){
		.name = "gcc_ce1_ahb_m_clk",
		@@ -2683,6 +2709,10 @@ static struct clk_regmap *gcc_falcon_clocks[] = {
		[GCC_UFS_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_ice_core_hw_ctl_clk.clkr,
		[GCC_UFS_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_aux_hw_ctl_clk.clkr,
		[GCC_UFS_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_unipro_core_hw_ctl_clk.clkr,
		[HLOS1_VOTE_TURING_ADSP_SMMU_CLK] =
		&hlos1_vote_turing_adsp_smmu_clk.clkr,
		[HLOS2_VOTE_TURING_ADSP_SMMU_CLK] =
		&hlos2_vote_turing_adsp_smmu_clk.clkr,
		};

		static const struct qcom_reset_map gcc_falcon_resets[] = {

+2 −0

Original line number	Diff line number	Diff line
		@@ -195,6 +195,8 @@
		#define GCC_UFS_ICE_CORE_HW_CTL_CLK 180
		#define GCC_UFS_PHY_AUX_HW_CTL_CLK 181
		#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 182
		#define HLOS1_VOTE_TURING_ADSP_SMMU_CLK 183
		#define HLOS2_VOTE_TURING_ADSP_SMMU_CLK 184

		/* Block resets */
		#define GCC_QUSB2PHY_PRIM_BCR 0