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Commit 6eaec594 authored by Sungjun Park's avatar Sungjun Park Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Fix BT current leakage in msmcobalt MTP and CDP 



There is a current leakage on S5 and LDO XO RF rail during
BT sleep. To prevent the current leakage, L7A/L17A/L25A
should be on during BT sleep. So, change L7A/L17A/L25A LDOs
from pin control version to SW control not to follow HW_EN2.
RFCLK2 has not been turned off during sleep and caused
extra current penalty. For RFCLK2 to follow HW_EN2 pin control,
clk_rf_clk2_pin should be used.

Change-Id: Ie316941535f62afd75eac21280061b489e9196c1
Signed-off-by: default avatarSungjun Park <sjpark@codeaurora.org>
parent e9537554

arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -17,11 +17,11 @@ 
		compatible = "qca,wcn3990";

		qca,bt-vdd-io-supply = <&pmcobalt_s3>;

		qca,bt-vdd-xtal-supply = <&pmcobalt_s5>;

		qca,bt-vdd-core-supply = <&pmcobalt_l7_pin_ctrl>;

		qca,bt-vdd-pa-supply = <&pmcobalt_l17_pin_ctrl>;

		qca,bt-vdd-ldo-supply = <&pmcobalt_l25_pin_ctrl>;

		qca,bt-vdd-core-supply = <&pmcobalt_l7>;

		qca,bt-vdd-pa-supply = <&pmcobalt_l17>;

		qca,bt-vdd-ldo-supply = <&pmcobalt_l25>;

		qca,bt-chip-pwd-supply = <&pmicobalt_bob_pin1>;

		clocks = <&clock_gcc clk_rf_clk2>;

		clocks = <&clock_gcc clk_rf_clk2_pin>;

		clock-names = "rf_clk2";



		qca,bt-vdd-io-voltage-level = <1352000 1352000>;

arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -18,11 +18,11 @@ 
		compatible = "qca,wcn3990";

		qca,bt-vdd-io-supply = <&pmcobalt_s3>;

		qca,bt-vdd-xtal-supply = <&pmcobalt_s5>;

		qca,bt-vdd-core-supply = <&pmcobalt_l7_pin_ctrl>;

		qca,bt-vdd-pa-supply = <&pmcobalt_l17_pin_ctrl>;

		qca,bt-vdd-ldo-supply = <&pmcobalt_l25_pin_ctrl>;

		qca,bt-vdd-core-supply = <&pmcobalt_l7>;

		qca,bt-vdd-pa-supply = <&pmcobalt_l17>;

		qca,bt-vdd-ldo-supply = <&pmcobalt_l25>;

		qca,bt-chip-pwd-supply = <&pmicobalt_bob_pin1>;

		clocks = <&clock_gcc clk_rf_clk2>;

		clocks = <&clock_gcc clk_rf_clk2_pin>;

		clock-names = "rf_clk2";



		qca,bt-vdd-io-voltage-level = <1352000 1352000>;