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Commit 6cf98d6e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes 

* 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel:
  drm/i915: pch_irq_handler -> {ibx, cpt}_irq_handler
  char/agp: add another Ironlake host bridge
  drm/i915: fix up ivb plane 3 pageflips
  drm/i915: hold forcewake around ring hw init
  drm/i915: Mark the ringbuffers as being in the GTT domain
  drm/i915/crt: Do not rely upon the HPD presence pin
  drm/i915: Reset last_retired_head when resetting ring
parents 7aaa61b3 23e81d69

drivers/char/agp/intel-agp.c

+1 −0
Original line number Diff line number Diff line
@@ -898,6 +898,7 @@ static struct pci_device_id agp_intel_pci_table[] = { 
	ID(PCI_DEVICE_ID_INTEL_B43_HB),

	ID(PCI_DEVICE_ID_INTEL_B43_1_HB),

	ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),

	ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB),

	ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),

	ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),

	ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),

drivers/char/agp/intel-agp.h

+1 −0
Original line number Diff line number Diff line
@@ -212,6 +212,7 @@ 
#define PCI_DEVICE_ID_INTEL_G41_HB          0x2E30

#define PCI_DEVICE_ID_INTEL_G41_IG          0x2E32

#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB	    0x0040

#define PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB	    0x0069

#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG	    0x0042

#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB	    0x0044

#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB	    0x0062

drivers/gpu/drm/i915/i915_drv.c

+9 −4
Original line number Diff line number Diff line
@@ -233,6 +233,7 @@ static const struct intel_device_info intel_sandybridge_d_info = { 
	.has_blt_ring = 1,

	.has_llc = 1,

	.has_pch_split = 1,

	.has_force_wake = 1,

};



static const struct intel_device_info intel_sandybridge_m_info = {
@@ -243,6 +244,7 @@ static const struct intel_device_info intel_sandybridge_m_info = { 
	.has_blt_ring = 1,

	.has_llc = 1,

	.has_pch_split = 1,

	.has_force_wake = 1,

};



static const struct intel_device_info intel_ivybridge_d_info = {
@@ -252,6 +254,7 @@ static const struct intel_device_info intel_ivybridge_d_info = { 
	.has_blt_ring = 1,

	.has_llc = 1,

	.has_pch_split = 1,

	.has_force_wake = 1,

};



static const struct intel_device_info intel_ivybridge_m_info = {
@@ -262,6 +265,7 @@ static const struct intel_device_info intel_ivybridge_m_info = { 
	.has_blt_ring = 1,

	.has_llc = 1,

	.has_pch_split = 1,

	.has_force_wake = 1,

};



static const struct intel_device_info intel_valleyview_m_info = {
@@ -289,6 +293,7 @@ static const struct intel_device_info intel_haswell_d_info = { 
	.has_blt_ring = 1,

	.has_llc = 1,

	.has_pch_split = 1,

	.has_force_wake = 1,

};



static const struct intel_device_info intel_haswell_m_info = {
@@ -298,6 +303,7 @@ static const struct intel_device_info intel_haswell_m_info = { 
	.has_blt_ring = 1,

	.has_llc = 1,

	.has_pch_split = 1,

	.has_force_wake = 1,

};



static const struct pci_device_id pciidlist[] = {		/* aka */
@@ -1139,10 +1145,9 @@ MODULE_LICENSE("GPL and additional rights"); 


/* We give fast paths for the really cool registers */

#define NEEDS_FORCE_WAKE(dev_priv, reg) \

       (((dev_priv)->info->gen >= 6) && \

	((HAS_FORCE_WAKE((dev_priv)->dev)) && \

	 ((reg) < 0x40000) &&            \

        ((reg) != FORCEWAKE)) && \

       (!IS_VALLEYVIEW((dev_priv)->dev))

	 ((reg) != FORCEWAKE))



#define __i915_read(x, y) \

u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \

drivers/gpu/drm/i915/i915_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -285,6 +285,7 @@ struct intel_device_info { 
	u8 is_ivybridge:1;

	u8 is_valleyview:1;

	u8 has_pch_split:1;

	u8 has_force_wake:1;

	u8 is_haswell:1;

	u8 has_fbc:1;

	u8 has_pipe_cxsr:1;
@@ -1101,6 +1102,8 @@ struct drm_i915_file_private { 
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)

#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)



#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)



#include "i915_trace.h"



/**

drivers/gpu/drm/i915/i915_irq.c

+35 −3
Original line number Diff line number Diff line
@@ -510,7 +510,7 @@ out: 
	return ret;

}



static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)

static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)

{

	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

	int pipe;
@@ -550,6 +550,35 @@ static void pch_irq_handler(struct drm_device *dev, u32 pch_iir) 
		DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");

}



static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)

{

	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

	int pipe;



	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)

		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",

				 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>

				 SDE_AUDIO_POWER_SHIFT_CPT);



	if (pch_iir & SDE_AUX_MASK_CPT)

		DRM_DEBUG_DRIVER("AUX channel interrupt\n");



	if (pch_iir & SDE_GMBUS_CPT)

		DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");



	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)

		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");



	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)

		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");



	if (pch_iir & SDE_FDI_MASK_CPT)

		for_each_pipe(pipe)

			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",

					 pipe_name(pipe),

					 I915_READ(FDI_RX_IIR(pipe)));

}



static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)

{

	struct drm_device *dev = (struct drm_device *) arg;
@@ -591,7 +620,7 @@ static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) 


			if (pch_iir & SDE_HOTPLUG_MASK_CPT)

				queue_work(dev_priv->wq, &dev_priv->hotplug_work);

			pch_irq_handler(dev, pch_iir);

			cpt_irq_handler(dev, pch_iir);



			/* clear PCH hotplug event before clear CPU irq */

			I915_WRITE(SDEIIR, pch_iir);
@@ -684,7 +713,10 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) 
	if (de_iir & DE_PCH_EVENT) {

		if (pch_iir & hotplug_mask)

			queue_work(dev_priv->wq, &dev_priv->hotplug_work);

		pch_irq_handler(dev, pch_iir);

		if (HAS_PCH_CPT(dev))

			cpt_irq_handler(dev, pch_iir);

		else

			ibx_irq_handler(dev, pch_iir);

	}



	if (de_iir & DE_PCU_EVENT) {