Loading drivers/gpu/drm/msm/adreno/a5xx_gpu.c +2 −4 Original line number Diff line number Diff line Loading @@ -481,10 +481,8 @@ static struct drm_gem_object *a5xx_ucode_load_bo(struct msm_gpu *gpu, struct drm_gem_object *bo; void *ptr; mutex_lock(&drm->struct_mutex); bo = msm_gem_new(drm, fw->size - 4, MSM_BO_UNCACHED | MSM_BO_GPU_READONLY); mutex_unlock(&drm->struct_mutex); if (IS_ERR(bo)) return bo; Loading Loading @@ -1408,8 +1406,8 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) * Set the user domain range to fall into the TTBR1 region for global * objects */ a5xx_config.va_start = 0x800000000; a5xx_config.va_end = 0x8ffffffff; a5xx_config.va_start = 0xfffffff000000000ULL; a5xx_config.va_end = 0xffffffffffffffffULL; a5xx_config.secure_va_start = SECURE_VA_START; a5xx_config.secure_va_end = SECURE_VA_START + SECURE_VA_SIZE - 1; Loading drivers/gpu/drm/msm/adreno/a5xx_power.c +0 −2 Original line number Diff line number Diff line Loading @@ -458,10 +458,8 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu) */ bosize = (cmds_size + (cmds_size / TYPE4_MAX_PAYLOAD) + 1) << 2; mutex_lock(&drm->struct_mutex); a5xx_gpu->gpmu_bo = msm_gem_new(drm, bosize, MSM_BO_UNCACHED | MSM_BO_GPU_READONLY); mutex_unlock(&drm->struct_mutex); if (IS_ERR(a5xx_gpu->gpmu_bo)) goto err; Loading drivers/gpu/drm/msm/adreno/a5xx_preempt.c +0 −2 Original line number Diff line number Diff line Loading @@ -24,9 +24,7 @@ static void *alloc_kernel_bo(struct drm_device *drm, struct msm_gpu *gpu, void *ptr; int ret; mutex_lock(&drm->struct_mutex); _bo = msm_gem_new(drm, size, flags); mutex_unlock(&drm->struct_mutex); if (IS_ERR(_bo)) return _bo; Loading drivers/gpu/drm/msm/adreno/a5xx_snapshot.c +4 −3 Original line number Diff line number Diff line Loading @@ -217,18 +217,19 @@ static int crashdump_init(struct msm_gpu *gpu, struct crashdump *crashdump) struct drm_device *drm = gpu->dev; int ret = -ENOMEM; crashdump->bo = msm_gem_new(drm, CRASHDUMP_BO_SIZE, MSM_BO_UNCACHED); crashdump->bo = msm_gem_new_locked(drm, CRASHDUMP_BO_SIZE, MSM_BO_UNCACHED); if (IS_ERR(crashdump->bo)) { ret = PTR_ERR(crashdump->bo); crashdump->bo = NULL; return ret; } crashdump->ptr = msm_gem_vaddr_locked(crashdump->bo); crashdump->ptr = msm_gem_vaddr(crashdump->bo); if (!crashdump->ptr) goto out; ret = msm_gem_get_iova_locked(crashdump->bo, gpu->aspace, ret = msm_gem_get_iova(crashdump->bo, gpu->aspace, &crashdump->iova); out: Loading drivers/gpu/drm/msm/adreno/adreno_gpu.c +0 −2 Original line number Diff line number Diff line Loading @@ -563,10 +563,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, } } mutex_lock(&drm->struct_mutex); adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs), MSM_BO_UNCACHED); mutex_unlock(&drm->struct_mutex); if (IS_ERR(adreno_gpu->memptrs_bo)) { ret = PTR_ERR(adreno_gpu->memptrs_bo); adreno_gpu->memptrs_bo = NULL; Loading Loading
drivers/gpu/drm/msm/adreno/a5xx_gpu.c +2 −4 Original line number Diff line number Diff line Loading @@ -481,10 +481,8 @@ static struct drm_gem_object *a5xx_ucode_load_bo(struct msm_gpu *gpu, struct drm_gem_object *bo; void *ptr; mutex_lock(&drm->struct_mutex); bo = msm_gem_new(drm, fw->size - 4, MSM_BO_UNCACHED | MSM_BO_GPU_READONLY); mutex_unlock(&drm->struct_mutex); if (IS_ERR(bo)) return bo; Loading Loading @@ -1408,8 +1406,8 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) * Set the user domain range to fall into the TTBR1 region for global * objects */ a5xx_config.va_start = 0x800000000; a5xx_config.va_end = 0x8ffffffff; a5xx_config.va_start = 0xfffffff000000000ULL; a5xx_config.va_end = 0xffffffffffffffffULL; a5xx_config.secure_va_start = SECURE_VA_START; a5xx_config.secure_va_end = SECURE_VA_START + SECURE_VA_SIZE - 1; Loading
drivers/gpu/drm/msm/adreno/a5xx_power.c +0 −2 Original line number Diff line number Diff line Loading @@ -458,10 +458,8 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu) */ bosize = (cmds_size + (cmds_size / TYPE4_MAX_PAYLOAD) + 1) << 2; mutex_lock(&drm->struct_mutex); a5xx_gpu->gpmu_bo = msm_gem_new(drm, bosize, MSM_BO_UNCACHED | MSM_BO_GPU_READONLY); mutex_unlock(&drm->struct_mutex); if (IS_ERR(a5xx_gpu->gpmu_bo)) goto err; Loading
drivers/gpu/drm/msm/adreno/a5xx_preempt.c +0 −2 Original line number Diff line number Diff line Loading @@ -24,9 +24,7 @@ static void *alloc_kernel_bo(struct drm_device *drm, struct msm_gpu *gpu, void *ptr; int ret; mutex_lock(&drm->struct_mutex); _bo = msm_gem_new(drm, size, flags); mutex_unlock(&drm->struct_mutex); if (IS_ERR(_bo)) return _bo; Loading
drivers/gpu/drm/msm/adreno/a5xx_snapshot.c +4 −3 Original line number Diff line number Diff line Loading @@ -217,18 +217,19 @@ static int crashdump_init(struct msm_gpu *gpu, struct crashdump *crashdump) struct drm_device *drm = gpu->dev; int ret = -ENOMEM; crashdump->bo = msm_gem_new(drm, CRASHDUMP_BO_SIZE, MSM_BO_UNCACHED); crashdump->bo = msm_gem_new_locked(drm, CRASHDUMP_BO_SIZE, MSM_BO_UNCACHED); if (IS_ERR(crashdump->bo)) { ret = PTR_ERR(crashdump->bo); crashdump->bo = NULL; return ret; } crashdump->ptr = msm_gem_vaddr_locked(crashdump->bo); crashdump->ptr = msm_gem_vaddr(crashdump->bo); if (!crashdump->ptr) goto out; ret = msm_gem_get_iova_locked(crashdump->bo, gpu->aspace, ret = msm_gem_get_iova(crashdump->bo, gpu->aspace, &crashdump->iova); out: Loading
drivers/gpu/drm/msm/adreno/adreno_gpu.c +0 −2 Original line number Diff line number Diff line Loading @@ -563,10 +563,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, } } mutex_lock(&drm->struct_mutex); adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs), MSM_BO_UNCACHED); mutex_unlock(&drm->struct_mutex); if (IS_ERR(adreno_gpu->memptrs_bo)) { ret = PTR_ERR(adreno_gpu->memptrs_bo); adreno_gpu->memptrs_bo = NULL; Loading